bit_cnt.v

Quartus开发环境下开发的Arinc 429总线收发器工程

// WARNING: Do NOT edit the input and output ports in this file in a text
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// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
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// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
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// limited to  modification,  reverse engineering,  de-compiling, or use  with
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// Generated by Quartus II Version 4.1 (Build Build 181 06/29/2004)
// Created on Mon Mar 10 10:51:50 2008

//  Module Declaration
module bit_cnt
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	rst_n, bc_crt, clk_in, bclk, eos, bit_clk
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input bc_crt;
	input rst_n;
	input bclk;
	input clk_in;
	
	output eos;
	output bit_clk;
	
	
	wire eos0;
	reg[4:0] bit_counter;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

always @(negedge rst_n or posedge (~bclk & bc_crt)) begin
   if (!rst_n) begin
    bit_counter<=5'd31;
   end
    else begin
    bit_counter<=bit_counter-5'd1;
   end
end

assign bit_clk=(~bclk & bc_crt);

R_SY_D_FF1 d1(1'd1,((bit_counter==5'd0)&& bc_crt), bclk,  eos0 );
R_SY_D_FF1 d2(clk_in, eos0, bclk,  eos );

endmodule


module	R_SY_D_FF1	( RB, D, CLK, Q );
input	RB, D, CLK;
output	Q;
reg	Q;
	always	@( posedge CLK or negedge RB ) begin
	if (!RB) 
	Q <=1'd0;
	else 
	 Q <=D;
	end
endmodule