data_sfr.v

Quartus开发环境下开发的Arinc 429总线收发器工程

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.


// Generated by Quartus II Version 4.1 (Build Build 181 06/29/2004)
// Created on Tue Mar 11 17:29:39 2008

//  Module Declaration
module data_sfr
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	rst_n, eos ,bit_clk, ones1_data, par_chec, data
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input bit_clk;
	input ones1_data;
	input rst_n;
	input eos;
	output [31:0] data;
	output   par_chec;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

    reg [31:0] data_out;
    reg        par_chec;
always @(negedge rst_n or posedge bit_clk or posedge eos) begin
  if (!rst_n || eos)
  par_chec<=1'd0;
  
  else begin
     data_out <= {data_out[30:0], ones1_data} ;
     par_chec<= par_chec+ones1_data  ;
  end
end

data_lath data_lath1(eos,  data_out, par_chec, data);

endmodule

module data_lath
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	eos,  data_out, par_chec, data
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input eos;
	input par_chec;
	input eos;
	input [31:0] data_out;
	
	output[31:0] data;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

    reg [31:0] data;
    reg        par_chec;
always @(posedge eos ) 
   data <={data_out[31:1], ~par_chec};
  
endmodule