dffpipe_h62.tdf

Quartus开发环境下开发的Arinc 429总线收发器工程

--dffpipe WIDTH=5 clock d q
--VERSION_BEGIN 4.1 cbx_mgl 2004:06:17:17:30:06:SJ cbx_stratixii 2004:05:18:11:28:28:SJ cbx_util 2004:03:29:17:03:30:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
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--synthesis_resources = lut 5 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_h62
( 
	clock	:	input;
	d[4..0]	:	input;
	q[4..0]	:	output;
) 
VARIABLE 
	dffe3a[4..0] : dffe;
	clrn	: NODE;
	ena	: NODE;
	prn	: NODE;
	sclr	: NODE;

BEGIN 
	dffe3a[].CLK = clock;
	dffe3a[].CLRN = clrn;
	dffe3a[].D = (d[] & (! sclr));
	dffe3a[].ENA = ena;
	dffe3a[].PRN = prn;
	clrn = VCC;
	ena = VCC;
	prn = VCC;
	q[] = dffe3a[].Q;
	sclr = GND;
END;
--VALID FILE