429_enc_dec.hier_info

Quartus开发环境下开发的Arinc 429总线收发器工程

address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
address_b[4] => ram_block1a16.PORTBADDR4
address_b[4] => ram_block1a17.PORTBADDR4
address_b[4] => ram_block1a18.PORTBADDR4
address_b[4] => ram_block1a19.PORTBADDR4
address_b[4] => ram_block1a20.PORTBADDR4
address_b[4] => ram_block1a21.PORTBADDR4
address_b[4] => ram_block1a22.PORTBADDR4
address_b[4] => ram_block1a23.PORTBADDR4
address_b[4] => ram_block1a24.PORTBADDR4
address_b[4] => ram_block1a25.PORTBADDR4
address_b[4] => ram_block1a26.PORTBADDR4
address_b[4] => ram_block1a27.PORTBADDR4
address_b[4] => ram_block1a28.PORTBADDR4
address_b[4] => ram_block1a29.PORTBADDR4
address_b[4] => ram_block1a30.PORTBADDR4
address_b[4] => ram_block1a31.PORTBADDR4
addressstall_b => ram_block1a0.PORTBADDRSTALL
addressstall_b => ram_block1a1.PORTBADDRSTALL
addressstall_b => ram_block1a2.PORTBADDRSTALL
addressstall_b => ram_block1a3.PORTBADDRSTALL
addressstall_b => ram_block1a4.PORTBADDRSTALL
addressstall_b => ram_block1a5.PORTBADDRSTALL
addressstall_b => ram_block1a6.PORTBADDRSTALL
addressstall_b => ram_block1a7.PORTBADDRSTALL
addressstall_b => ram_block1a8.PORTBADDRSTALL
addressstall_b => ram_block1a9.PORTBADDRSTALL
addressstall_b => ram_block1a10.PORTBADDRSTALL
addressstall_b => ram_block1a11.PORTBADDRSTALL
addressstall_b => ram_block1a12.PORTBADDRSTALL
addressstall_b => ram_block1a13.PORTBADDRSTALL
addressstall_b => ram_block1a14.PORTBADDRSTALL
addressstall_b => ram_block1a15.PORTBADDRSTALL
addressstall_b => ram_block1a16.PORTBADDRSTALL
addressstall_b => ram_block1a17.PORTBADDRSTALL
addressstall_b => ram_block1a18.PORTBADDRSTALL
addressstall_b => ram_block1a19.PORTBADDRSTALL
addressstall_b => ram_block1a20.PORTBADDRSTALL
addressstall_b => ram_block1a21.PORTBADDRSTALL
addressstall_b => ram_block1a22.PORTBADDRSTALL
addressstall_b => ram_block1a23.PORTBADDRSTALL
addressstall_b => ram_block1a24.PORTBADDRSTALL
addressstall_b => ram_block1a25.PORTBADDRSTALL
addressstall_b => ram_block1a26.PORTBADDRSTALL
addressstall_b => ram_block1a27.PORTBADDRSTALL
addressstall_b => ram_block1a28.PORTBADDRSTALL
addressstall_b => ram_block1a29.PORTBADDRSTALL
addressstall_b => ram_block1a30.PORTBADDRSTALL
addressstall_b => ram_block1a31.PORTBADDRSTALL
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
clock1 => ram_block1a8.CLK1
clock1 => ram_block1a9.CLK1
clock1 => ram_block1a10.CLK1
clock1 => ram_block1a11.CLK1
clock1 => ram_block1a12.CLK1
clock1 => ram_block1a13.CLK1
clock1 => ram_block1a14.CLK1
clock1 => ram_block1a15.CLK1
clock1 => ram_block1a16.CLK1
clock1 => ram_block1a17.CLK1
clock1 => ram_block1a18.CLK1
clock1 => ram_block1a19.CLK1
clock1 => ram_block1a20.CLK1
clock1 => ram_block1a21.CLK1
clock1 => ram_block1a22.CLK1
clock1 => ram_block1a23.CLK1
clock1 => ram_block1a24.CLK1
clock1 => ram_block1a25.CLK1
clock1 => ram_block1a26.CLK1
clock1 => ram_block1a27.CLK1
clock1 => ram_block1a28.CLK1
clock1 => ram_block1a29.CLK1
clock1 => ram_block1a30.CLK1
clock1 => ram_block1a31.CLK1
clocken1 => ram_block1a0.ENA1
clocken1 => ram_block1a1.ENA1
clocken1 => ram_block1a2.ENA1
clocken1 => ram_block1a3.ENA1
clocken1 => ram_block1a4.ENA1
clocken1 => ram_block1a5.ENA1
clocken1 => ram_block1a6.ENA1
clocken1 => ram_block1a7.ENA1
clocken1 => ram_block1a8.ENA1
clocken1 => ram_block1a9.ENA1
clocken1 => ram_block1a10.ENA1
clocken1 => ram_block1a11.ENA1
clocken1 => ram_block1a12.ENA1
clocken1 => ram_block1a13.ENA1
clocken1 => ram_block1a14.ENA1
clocken1 => ram_block1a15.ENA1
clocken1 => ram_block1a16.ENA1
clocken1 => ram_block1a17.ENA1
clocken1 => ram_block1a18.ENA1
clocken1 => ram_block1a19.ENA1
clocken1 => ram_block1a20.ENA1
clocken1 => ram_block1a21.ENA1
clocken1 => ram_block1a22.ENA1
clocken1 => ram_block1a23.ENA1
clocken1 => ram_block1a24.ENA1
clocken1 => ram_block1a25.ENA1
clocken1 => ram_block1a26.ENA1
clocken1 => ram_block1a27.ENA1
clocken1 => ram_block1a28.ENA1
clocken1 => ram_block1a29.ENA1
clocken1 => ram_block1a30.ENA1
clocken1 => ram_block1a31.ENA1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
data_a[16] => ram_block1a16.PORTADATAIN
data_a[17] => ram_block1a17.PORTADATAIN
data_a[18] => ram_block1a18.PORTADATAIN
data_a[19] => ram_block1a19.PORTADATAIN
data_a[20] => ram_block1a20.PORTADATAIN
data_a[21] => ram_block1a21.PORTADATAIN
data_a[22] => ram_block1a22.PORTADATAIN
data_a[23] => ram_block1a23.PORTADATAIN
data_a[24] => ram_block1a24.PORTADATAIN
data_a[25] => ram_block1a25.PORTADATAIN
data_a[26] => ram_block1a26.PORTADATAIN
data_a[27] => ram_block1a27.PORTADATAIN
data_a[28] => ram_block1a28.PORTADATAIN
data_a[29] => ram_block1a29.PORTADATAIN
data_a[30] => ram_block1a30.PORTADATAIN
data_a[31] => ram_block1a31.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
q_b[8] <= ram_block1a8.PORTBDATAOUT
q_b[9] <= ram_block1a9.PORTBDATAOUT
q_b[10] <= ram_block1a10.PORTBDATAOUT
q_b[11] <= ram_block1a11.PORTBDATAOUT
q_b[12] <= ram_block1a12.PORTBDATAOUT
q_b[13] <= ram_block1a13.PORTBDATAOUT
q_b[14] <= ram_block1a14.PORTBDATAOUT
q_b[15] <= ram_block1a15.PORTBDATAOUT
q_b[16] <= ram_block1a16.PORTBDATAOUT
q_b[17] <= ram_block1a17.PORTBDATAOUT
q_b[18] <= ram_block1a18.PORTBDATAOUT
q_b[19] <= ram_block1a19.PORTBDATAOUT
q_b[20] <= ram_block1a20.PORTBDATAOUT
q_b[21] <= ram_block1a21.PORTBDATAOUT
q_b[22] <= ram_block1a22.PORTBDATAOUT
q_b[23] <= ram_block1a23.PORTBDATAOUT
q_b[24] <= ram_block1a24.PORTBDATAOUT
q_b[25] <= ram_block1a25.PORTBDATAOUT
q_b[26] <= ram_block1a26.PORTBDATAOUT
q_b[27] <= ram_block1a27.PORTBDATAOUT
q_b[28] <= ram_block1a28.PORTBDATAOUT
q_b[29] <= ram_block1a29.PORTBDATAOUT
q_b[30] <= ram_block1a30.PORTBDATAOUT
q_b[31] <= ram_block1a31.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a16.PORTAWE
wren_a => ram_block1a17.PORTAWE
wren_a => ram_block1a18.PORTAWE
wren_a => ram_block1a19.PORTAWE
wren_a => ram_block1a20.PORTAWE
wren_a => ram_block1a21.PORTAWE
wren_a => ram_block1a22.PORTAWE
wren_a => ram_block1a23.PORTAWE
wren_a => ram_block1a24.PORTAWE
wren_a => ram_block1a25.PORTAWE
wren_a => ram_block1a26.PORTAWE
wren_a => ram_block1a27.PORTAWE
wren_a => ram_block1a28.PORTAWE
wren_a => ram_block1a29.PORTAWE
wren_a => ram_block1a30.PORTAWE
wren_a => ram_block1a31.PORTAWE


|429_enc_dec|lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|alt_synch_pipe_h62:rs_dgwp
clock => dffpipe_h62:dffpipe2.clock
d[0] => dffpipe_h62:dffpipe2.d[0]
d[1] => dffpipe_h62:dffpipe2.d[1]
d[2] => dffpipe_h62:dffpipe2.d[2]
d[3] => dffpipe_h62:dffpipe2.d[3]
d[4] => dffpipe_h62:dffpipe2.d[4]
q[0] <= dffpipe_h62:dffpipe2.q[0]
q[1] <= dffpipe_h62:dffpipe2.q[1]
q[2] <= dffpipe_h62:dffpipe2.q[2]
q[3] <= dffpipe_h62:dffpipe2.q[3]
q[4] <= dffpipe_h62:dffpipe2.q[4]


|429_enc_dec|lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|alt_synch_pipe_h62:rs_dgwp|dffpipe_h62:dffpipe2
clock => dffe3a[4].CLK
clock => dffe3a[3].CLK
clock => dffe3a[2].CLK
clock => dffe3a[1].CLK
clock => dffe3a[0].CLK
q[0] <= dffe3a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe3a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe3a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe3a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe3a[4].DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|dffpipe_er2:ws_brp
clock => dffe4a[4].CLK
clock => dffe4a[3].CLK
clock => dffe4a[2].CLK
clock => dffe4a[1].CLK
clock => dffe4a[0].CLK
q[0] <= dffe4a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe4a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe4a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe4a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe4a[4].DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|dffpipe_er2:ws_bwp
clock => dffe4a[4].CLK
clock => dffe4a[3].CLK
clock => dffe4a[2].CLK
clock => dffe4a[1].CLK
clock => dffe4a[0].CLK
q[0] <= dffe4a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe4a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe4a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe4a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe4a[4].DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|alt_synch_pipe_h62:ws_dgrp
clock => dffpipe_h62:dffpipe2.clock
d[0] => dffpipe_h62:dffpipe2.d[0]
d[1] => dffpipe_h62:dffpipe2.d[1]
d[2] => dffpipe_h62:dffpipe2.d[2]
d[3] => dffpipe_h62:dffpipe2.d[3]
d[4] => dffpipe_h62:dffpipe2.d[4]
q[0] <= dffpipe_h62:dffpipe2.q[0]
q[1] <= dffpipe_h62:dffpipe2.q[1]
q[2] <= dffpipe_h62:dffpipe2.q[2]
q[3] <= dffpipe_h62:dffpipe2.q[3]
q[4] <= dffpipe_h62:dffpipe2.q[4]


|429_enc_dec|lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|alt_synch_pipe_h62:ws_dgrp|dffpipe_h62:dffpipe2
clock => dffe3a[4].CLK
clock => dffe3a[3].CLK
clock => dffe3a[2].CLK
clock => dffe3a[1].CLK
clock => dffe3a[0].CLK
q[0] <= dffe3a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe3a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe3a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe3a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe3a[4].DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|add_sub_u5c:wrusedw_sub
dataa[0] => add_sub_cella[0].DATAA
dataa[1] => add_sub_cella[1].DATAA
dataa[2] => add_sub_cella[2].DATAA
dataa[3] => add_sub_cella[3].DATAA
dataa[4] => add_sub_cella[4].DATAA
datab[0] => add_sub_cella[0].DATAB
datab[1] => add_sub_cella[1].DATAB
datab[2] => add_sub_cella[2].DATAB
datab[3] => add_sub_cella[3].DATAB
datab[4] => add_sub_cella[4].DATAB
result[0] <= add_sub_cella[0].COMBOUT
result[1] <= add_sub_cella[1].COMBOUT
result[2] <= add_sub_cella[2].COMBOUT
result[3] <= add_sub_cella[3].COMBOUT
result[4] <= add_sub_cella[4].COMBOUT