429_enc_dec.hier_info

Quartus开发环境下开发的Arinc 429总线收发器工程

eos => data[12]~reg0.CLK
eos => data[11]~reg0.CLK
eos => data[10]~reg0.CLK
eos => data[9]~reg0.CLK
eos => data[8]~reg0.CLK
eos => data[7]~reg0.CLK
eos => data[6]~reg0.CLK
eos => data[5]~reg0.CLK
eos => data[4]~reg0.CLK
eos => data[3]~reg0.CLK
eos => data[2]~reg0.CLK
eos => data[1]~reg0.CLK
eos => data[0]~reg0.CLK
eos => data[31]~reg0.CLK
data_out[0] => ~NO_FANOUT~
data_out[1] => data[1]~reg0.DATAIN
data_out[2] => data[2]~reg0.DATAIN
data_out[3] => data[3]~reg0.DATAIN
data_out[4] => data[4]~reg0.DATAIN
data_out[5] => data[5]~reg0.DATAIN
data_out[6] => data[6]~reg0.DATAIN
data_out[7] => data[7]~reg0.DATAIN
data_out[8] => data[8]~reg0.DATAIN
data_out[9] => data[9]~reg0.DATAIN
data_out[10] => data[10]~reg0.DATAIN
data_out[11] => data[11]~reg0.DATAIN
data_out[12] => data[12]~reg0.DATAIN
data_out[13] => data[13]~reg0.DATAIN
data_out[14] => data[14]~reg0.DATAIN
data_out[15] => data[15]~reg0.DATAIN
data_out[16] => data[16]~reg0.DATAIN
data_out[17] => data[17]~reg0.DATAIN
data_out[18] => data[18]~reg0.DATAIN
data_out[19] => data[19]~reg0.DATAIN
data_out[20] => data[20]~reg0.DATAIN
data_out[21] => data[21]~reg0.DATAIN
data_out[22] => data[22]~reg0.DATAIN
data_out[23] => data[23]~reg0.DATAIN
data_out[24] => data[24]~reg0.DATAIN
data_out[25] => data[25]~reg0.DATAIN
data_out[26] => data[26]~reg0.DATAIN
data_out[27] => data[27]~reg0.DATAIN
data_out[28] => data[28]~reg0.DATAIN
data_out[29] => data[29]~reg0.DATAIN
data_out[30] => data[30]~reg0.DATAIN
data_out[31] => data[31]~reg0.DATAIN
par_chec => data[0]~reg0.DATAIN
data[0] <= data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[8] <= data[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[9] <= data[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[10] <= data[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[11] <= data[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[12] <= data[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[13] <= data[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[14] <= data[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[15] <= data[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[16] <= data[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[17] <= data[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[18] <= data[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[19] <= data[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[20] <= data[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[21] <= data[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[22] <= data[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[23] <= data[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[24] <= data[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[25] <= data[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[26] <= data[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[27] <= data[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[28] <= data[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[29] <= data[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[30] <= data[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[31] <= data[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|lpm_fifo0:inst9
data[0] => data[0]~31.IN1
data[1] => data[1]~30.IN1
data[2] => data[2]~29.IN1
data[3] => data[3]~28.IN1
data[4] => data[4]~27.IN1
data[5] => data[5]~26.IN1
data[6] => data[6]~25.IN1
data[7] => data[7]~24.IN1
data[8] => data[8]~23.IN1
data[9] => data[9]~22.IN1
data[10] => data[10]~21.IN1
data[11] => data[11]~20.IN1
data[12] => data[12]~19.IN1
data[13] => data[13]~18.IN1
data[14] => data[14]~17.IN1
data[15] => data[15]~16.IN1
data[16] => data[16]~15.IN1
data[17] => data[17]~14.IN1
data[18] => data[18]~13.IN1
data[19] => data[19]~12.IN1
data[20] => data[20]~11.IN1
data[21] => data[21]~10.IN1
data[22] => data[22]~9.IN1
data[23] => data[23]~8.IN1
data[24] => data[24]~7.IN1
data[25] => data[25]~6.IN1
data[26] => data[26]~5.IN1
data[27] => data[27]~4.IN1
data[28] => data[28]~3.IN1
data[29] => data[29]~2.IN1
data[30] => data[30]~1.IN1
data[31] => data[31]~0.IN1
wrreq => wrreq~0.IN1
rdreq => rdreq~0.IN1
rdclk => rdclk~0.IN1
wrclk => wrclk~0.IN1
q[0] <= dcfifo:dcfifo_component.q
q[1] <= dcfifo:dcfifo_component.q
q[2] <= dcfifo:dcfifo_component.q
q[3] <= dcfifo:dcfifo_component.q
q[4] <= dcfifo:dcfifo_component.q
q[5] <= dcfifo:dcfifo_component.q
q[6] <= dcfifo:dcfifo_component.q
q[7] <= dcfifo:dcfifo_component.q
q[8] <= dcfifo:dcfifo_component.q
q[9] <= dcfifo:dcfifo_component.q
q[10] <= dcfifo:dcfifo_component.q
q[11] <= dcfifo:dcfifo_component.q
q[12] <= dcfifo:dcfifo_component.q
q[13] <= dcfifo:dcfifo_component.q
q[14] <= dcfifo:dcfifo_component.q
q[15] <= dcfifo:dcfifo_component.q
q[16] <= dcfifo:dcfifo_component.q
q[17] <= dcfifo:dcfifo_component.q
q[18] <= dcfifo:dcfifo_component.q
q[19] <= dcfifo:dcfifo_component.q
q[20] <= dcfifo:dcfifo_component.q
q[21] <= dcfifo:dcfifo_component.q
q[22] <= dcfifo:dcfifo_component.q
q[23] <= dcfifo:dcfifo_component.q
q[24] <= dcfifo:dcfifo_component.q
q[25] <= dcfifo:dcfifo_component.q
q[26] <= dcfifo:dcfifo_component.q
q[27] <= dcfifo:dcfifo_component.q
q[28] <= dcfifo:dcfifo_component.q
q[29] <= dcfifo:dcfifo_component.q
q[30] <= dcfifo:dcfifo_component.q
q[31] <= dcfifo:dcfifo_component.q
rdempty <= dcfifo:dcfifo_component.rdempty
wrfull <= dcfifo:dcfifo_component.wrfull
wrusedw[0] <= dcfifo:dcfifo_component.wrusedw
wrusedw[1] <= dcfifo:dcfifo_component.wrusedw
wrusedw[2] <= dcfifo:dcfifo_component.wrusedw
wrusedw[3] <= dcfifo:dcfifo_component.wrusedw
wrusedw[4] <= dcfifo:dcfifo_component.wrusedw


|429_enc_dec|lpm_fifo0:inst9|dcfifo:dcfifo_component
data[0] => dcfifo_vos:auto_generated.data[0]
data[1] => dcfifo_vos:auto_generated.data[1]
data[2] => dcfifo_vos:auto_generated.data[2]
data[3] => dcfifo_vos:auto_generated.data[3]
data[4] => dcfifo_vos:auto_generated.data[4]
data[5] => dcfifo_vos:auto_generated.data[5]
data[6] => dcfifo_vos:auto_generated.data[6]
data[7] => dcfifo_vos:auto_generated.data[7]
data[8] => dcfifo_vos:auto_generated.data[8]
data[9] => dcfifo_vos:auto_generated.data[9]
data[10] => dcfifo_vos:auto_generated.data[10]
data[11] => dcfifo_vos:auto_generated.data[11]
data[12] => dcfifo_vos:auto_generated.data[12]
data[13] => dcfifo_vos:auto_generated.data[13]
data[14] => dcfifo_vos:auto_generated.data[14]
data[15] => dcfifo_vos:auto_generated.data[15]
data[16] => dcfifo_vos:auto_generated.data[16]
data[17] => dcfifo_vos:auto_generated.data[17]
data[18] => dcfifo_vos:auto_generated.data[18]
data[19] => dcfifo_vos:auto_generated.data[19]
data[20] => dcfifo_vos:auto_generated.data[20]
data[21] => dcfifo_vos:auto_generated.data[21]
data[22] => dcfifo_vos:auto_generated.data[22]
data[23] => dcfifo_vos:auto_generated.data[23]
data[24] => dcfifo_vos:auto_generated.data[24]
data[25] => dcfifo_vos:auto_generated.data[25]
data[26] => dcfifo_vos:auto_generated.data[26]
data[27] => dcfifo_vos:auto_generated.data[27]
data[28] => dcfifo_vos:auto_generated.data[28]
data[29] => dcfifo_vos:auto_generated.data[29]
data[30] => dcfifo_vos:auto_generated.data[30]
data[31] => dcfifo_vos:auto_generated.data[31]
q[0] <= dcfifo_vos:auto_generated.q[0]
q[1] <= dcfifo_vos:auto_generated.q[1]
q[2] <= dcfifo_vos:auto_generated.q[2]
q[3] <= dcfifo_vos:auto_generated.q[3]
q[4] <= dcfifo_vos:auto_generated.q[4]
q[5] <= dcfifo_vos:auto_generated.q[5]
q[6] <= dcfifo_vos:auto_generated.q[6]
q[7] <= dcfifo_vos:auto_generated.q[7]
q[8] <= dcfifo_vos:auto_generated.q[8]
q[9] <= dcfifo_vos:auto_generated.q[9]
q[10] <= dcfifo_vos:auto_generated.q[10]
q[11] <= dcfifo_vos:auto_generated.q[11]
q[12] <= dcfifo_vos:auto_generated.q[12]
q[13] <= dcfifo_vos:auto_generated.q[13]
q[14] <= dcfifo_vos:auto_generated.q[14]
q[15] <= dcfifo_vos:auto_generated.q[15]
q[16] <= dcfifo_vos:auto_generated.q[16]
q[17] <= dcfifo_vos:auto_generated.q[17]
q[18] <= dcfifo_vos:auto_generated.q[18]
q[19] <= dcfifo_vos:auto_generated.q[19]
q[20] <= dcfifo_vos:auto_generated.q[20]
q[21] <= dcfifo_vos:auto_generated.q[21]
q[22] <= dcfifo_vos:auto_generated.q[22]
q[23] <= dcfifo_vos:auto_generated.q[23]
q[24] <= dcfifo_vos:auto_generated.q[24]
q[25] <= dcfifo_vos:auto_generated.q[25]
q[26] <= dcfifo_vos:auto_generated.q[26]
q[27] <= dcfifo_vos:auto_generated.q[27]
q[28] <= dcfifo_vos:auto_generated.q[28]
q[29] <= dcfifo_vos:auto_generated.q[29]
q[30] <= dcfifo_vos:auto_generated.q[30]
q[31] <= dcfifo_vos:auto_generated.q[31]
rdclk => dcfifo_vos:auto_generated.rdclk
rdreq => dcfifo_vos:auto_generated.rdreq
wrclk => dcfifo_vos:auto_generated.wrclk
wrreq => dcfifo_vos:auto_generated.wrreq
aclr => ~NO_FANOUT~
rdempty <= dcfifo_vos:auto_generated.rdempty
rdfull <= <UNC>
wrempty <= <UNC>
wrfull <= dcfifo_vos:auto_generated.wrfull
rdusedw[0] <= <UNC>
rdusedw[1] <= <UNC>
rdusedw[2] <= <UNC>
rdusedw[3] <= <UNC>
rdusedw[4] <= <UNC>
wrusedw[0] <= dcfifo_vos:auto_generated.wrusedw[0]
wrusedw[1] <= dcfifo_vos:auto_generated.wrusedw[1]
wrusedw[2] <= dcfifo_vos:auto_generated.wrusedw[2]
wrusedw[3] <= dcfifo_vos:auto_generated.wrusedw[3]
wrusedw[4] <= dcfifo_vos:auto_generated.wrusedw[4]


|429_enc_dec|lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated
data[0] => altsyncram_2hp:fifo_ram.data_a[0]
data[1] => altsyncram_2hp:fifo_ram.data_a[1]
data[2] => altsyncram_2hp:fifo_ram.data_a[2]
data[3] => altsyncram_2hp:fifo_ram.data_a[3]
data[4] => altsyncram_2hp:fifo_ram.data_a[4]
data[5] => altsyncram_2hp:fifo_ram.data_a[5]
data[6] => altsyncram_2hp:fifo_ram.data_a[6]
data[7] => altsyncram_2hp:fifo_ram.data_a[7]
data[8] => altsyncram_2hp:fifo_ram.data_a[8]
data[9] => altsyncram_2hp:fifo_ram.data_a[9]
data[10] => altsyncram_2hp:fifo_ram.data_a[10]
data[11] => altsyncram_2hp:fifo_ram.data_a[11]
data[12] => altsyncram_2hp:fifo_ram.data_a[12]
data[13] => altsyncram_2hp:fifo_ram.data_a[13]
data[14] => altsyncram_2hp:fifo_ram.data_a[14]
data[15] => altsyncram_2hp:fifo_ram.data_a[15]
data[16] => altsyncram_2hp:fifo_ram.data_a[16]
data[17] => altsyncram_2hp:fifo_ram.data_a[17]
data[18] => altsyncram_2hp:fifo_ram.data_a[18]
data[19] => altsyncram_2hp:fifo_ram.data_a[19]
data[20] => altsyncram_2hp:fifo_ram.data_a[20]
data[21] => altsyncram_2hp:fifo_ram.data_a[21]
data[22] => altsyncram_2hp:fifo_ram.data_a[22]
data[23] => altsyncram_2hp:fifo_ram.data_a[23]
data[24] => altsyncram_2hp:fifo_ram.data_a[24]
data[25] => altsyncram_2hp:fifo_ram.data_a[25]
data[26] => altsyncram_2hp:fifo_ram.data_a[26]
data[27] => altsyncram_2hp:fifo_ram.data_a[27]
data[28] => altsyncram_2hp:fifo_ram.data_a[28]
data[29] => altsyncram_2hp:fifo_ram.data_a[29]
data[30] => altsyncram_2hp:fifo_ram.data_a[30]
data[31] => altsyncram_2hp:fifo_ram.data_a[31]
q[0] <= altsyncram_2hp:fifo_ram.q_b[0]
q[1] <= altsyncram_2hp:fifo_ram.q_b[1]
q[2] <= altsyncram_2hp:fifo_ram.q_b[2]
q[3] <= altsyncram_2hp:fifo_ram.q_b[3]
q[4] <= altsyncram_2hp:fifo_ram.q_b[4]
q[5] <= altsyncram_2hp:fifo_ram.q_b[5]
q[6] <= altsyncram_2hp:fifo_ram.q_b[6]
q[7] <= altsyncram_2hp:fifo_ram.q_b[7]
q[8] <= altsyncram_2hp:fifo_ram.q_b[8]
q[9] <= altsyncram_2hp:fifo_ram.q_b[9]
q[10] <= altsyncram_2hp:fifo_ram.q_b[10]
q[11] <= altsyncram_2hp:fifo_ram.q_b[11]
q[12] <= altsyncram_2hp:fifo_ram.q_b[12]
q[13] <= altsyncram_2hp:fifo_ram.q_b[13]
q[14] <= altsyncram_2hp:fifo_ram.q_b[14]
q[15] <= altsyncram_2hp:fifo_ram.q_b[15]
q[16] <= altsyncram_2hp:fifo_ram.q_b[16]
q[17] <= altsyncram_2hp:fifo_ram.q_b[17]
q[18] <= altsyncram_2hp:fifo_ram.q_b[18]
q[19] <= altsyncram_2hp:fifo_ram.q_b[19]
q[20] <= altsyncram_2hp:fifo_ram.q_b[20]
q[21] <= altsyncram_2hp:fifo_ram.q_b[21]
q[22] <= altsyncram_2hp:fifo_ram.q_b[22]
q[23] <= altsyncram_2hp:fifo_ram.q_b[23]
q[24] <= altsyncram_2hp:fifo_ram.q_b[24]
q[25] <= altsyncram_2hp:fifo_ram.q_b[25]
q[26] <= altsyncram_2hp:fifo_ram.q_b[26]
q[27] <= altsyncram_2hp:fifo_ram.q_b[27]
q[28] <= altsyncram_2hp:fifo_ram.q_b[28]
q[29] <= altsyncram_2hp:fifo_ram.q_b[29]
q[30] <= altsyncram_2hp:fifo_ram.q_b[30]
q[31] <= altsyncram_2hp:fifo_ram.q_b[31]
rdclk => a_graycounter_aq5:rdptr_g1p.clock
rdclk => altsyncram_2hp:fifo_ram.clock1
rdclk => alt_synch_pipe_h62:rs_dgwp.clock
rdclk => p0addr.CLK
rdclk => rdptr_g[4].CLK
rdclk => rdptr_g[3].CLK
rdclk => rdptr_g[2].CLK
rdclk => rdptr_g[1].CLK
rdclk => rdptr_g[0].CLK
rdempty <= rdempty_eq_comp_aeb_int.DB_MAX_OUTPUT_PORT_TYPE
rdreq => valid_rdreq.IN0
wrclk => a_graycounter_5j6:wrptr_g1p.clock
wrclk => altsyncram_2hp:fifo_ram.clock0
wrclk => dffpipe_er2:ws_brp.clock
wrclk => dffpipe_er2:ws_bwp.clock
wrclk => alt_synch_pipe_h62:ws_dgrp.clock
wrclk => delayed_wrptr_g[4].CLK
wrclk => delayed_wrptr_g[3].CLK
wrclk => delayed_wrptr_g[2].CLK
wrclk => delayed_wrptr_g[1].CLK
wrclk => delayed_wrptr_g[0].CLK
wrclk => wrptr_g[4].CLK
wrclk => wrptr_g[3].CLK
wrclk => wrptr_g[2].CLK
wrclk => wrptr_g[1].CLK
wrclk => wrptr_g[0].CLK
wrfull <= wrfull_eq_comp_aeb_int.DB_MAX_OUTPUT_PORT_TYPE
wrreq => valid_wrreq.IN0
wrusedw[0] <= add_sub_u5c:wrusedw_sub.result[0]
wrusedw[1] <= add_sub_u5c:wrusedw_sub.result[1]
wrusedw[2] <= add_sub_u5c:wrusedw_sub.result[2]
wrusedw[3] <= add_sub_u5c:wrusedw_sub.result[3]
wrusedw[4] <= add_sub_u5c:wrusedw_sub.result[4]


|429_enc_dec|lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|a_gray2bin_8cb:wrptr_g_gray2bin
bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
bin[4] <= gray[4].DB_MAX_OUTPUT_PORT_TYPE