429_enc_dec.hier_info

Quartus开发环境下开发的Arinc 429总线收发器工程

|429_enc_dec
clk_in <= clk_div:inst1.clk_in
clk => clk_div:inst1.clk
cr0 => clk_div:inst1.clk_rate
rst_n => clk_div:inst1.rst_n
rst_n => null1sfr:inst3.rst_n
rst_n => zerossfr:inst4.rst_n
rst_n => onessfr:inst2.rst_n
rst_n => seq_ctr:inst6.rst_n
rst_n => bit_cnt:inst7.rst_n
rst_n => word_gap_timer:inst5.rst_n
rst_n => data_sfr:inst8.rst_n
rst_n => inst11.IN1
rst_n => lpm_fifo0:inst9.wrreq
rst_n => lpm_fifo0:inst9.rdreq
word_gap <= word_gap_timer:inst5.word_gap
rn1b => rx_input:inst.rnb
rn1a => rx_input:inst.rna
eos <= bit_cnt:inst7.eos
bit_clk <= bit_cnt:inst7.bit_clk
par_chec <= data_sfr:inst8.par_chec
wrclk <= inst11.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= data_sfr:inst8.data[0]
data[1] <= data_sfr:inst8.data[1]
data[2] <= data_sfr:inst8.data[2]
data[3] <= data_sfr:inst8.data[3]
data[4] <= data_sfr:inst8.data[4]
data[5] <= data_sfr:inst8.data[5]
data[6] <= data_sfr:inst8.data[6]
data[7] <= data_sfr:inst8.data[7]
data[8] <= data_sfr:inst8.data[8]
data[9] <= data_sfr:inst8.data[9]
data[10] <= data_sfr:inst8.data[10]
data[11] <= data_sfr:inst8.data[11]
data[12] <= data_sfr:inst8.data[12]
data[13] <= data_sfr:inst8.data[13]
data[14] <= data_sfr:inst8.data[14]
data[15] <= data_sfr:inst8.data[15]
data[16] <= data_sfr:inst8.data[16]
data[17] <= data_sfr:inst8.data[17]
data[18] <= data_sfr:inst8.data[18]
data[19] <= data_sfr:inst8.data[19]
data[20] <= data_sfr:inst8.data[20]
data[21] <= data_sfr:inst8.data[21]
data[22] <= data_sfr:inst8.data[22]
data[23] <= data_sfr:inst8.data[23]
data[24] <= data_sfr:inst8.data[24]
data[25] <= data_sfr:inst8.data[25]
data[26] <= data_sfr:inst8.data[26]
data[27] <= data_sfr:inst8.data[27]
data[28] <= data_sfr:inst8.data[28]
data[29] <= data_sfr:inst8.data[29]
data[30] <= data_sfr:inst8.data[30]
data[31] <= data_sfr:inst8.data[31]
q[0] <= lpm_fifo0:inst9.q[0]
q[1] <= lpm_fifo0:inst9.q[1]
q[2] <= lpm_fifo0:inst9.q[2]
q[3] <= lpm_fifo0:inst9.q[3]
q[4] <= lpm_fifo0:inst9.q[4]
q[5] <= lpm_fifo0:inst9.q[5]
q[6] <= lpm_fifo0:inst9.q[6]
q[7] <= lpm_fifo0:inst9.q[7]
q[8] <= lpm_fifo0:inst9.q[8]
q[9] <= lpm_fifo0:inst9.q[9]
q[10] <= lpm_fifo0:inst9.q[10]
q[11] <= lpm_fifo0:inst9.q[11]
q[12] <= lpm_fifo0:inst9.q[12]
q[13] <= lpm_fifo0:inst9.q[13]
q[14] <= lpm_fifo0:inst9.q[14]
q[15] <= lpm_fifo0:inst9.q[15]
q[16] <= lpm_fifo0:inst9.q[16]
q[17] <= lpm_fifo0:inst9.q[17]
q[18] <= lpm_fifo0:inst9.q[18]
q[19] <= lpm_fifo0:inst9.q[19]
q[20] <= lpm_fifo0:inst9.q[20]
q[21] <= lpm_fifo0:inst9.q[21]
q[22] <= lpm_fifo0:inst9.q[22]
q[23] <= lpm_fifo0:inst9.q[23]
q[24] <= lpm_fifo0:inst9.q[24]
q[25] <= lpm_fifo0:inst9.q[25]
q[26] <= lpm_fifo0:inst9.q[26]
q[27] <= lpm_fifo0:inst9.q[27]
q[28] <= lpm_fifo0:inst9.q[28]
q[29] <= lpm_fifo0:inst9.q[29]
q[30] <= lpm_fifo0:inst9.q[30]
q[31] <= lpm_fifo0:inst9.q[31]
rdclk => lpm_fifo0:inst9.rdclk
wrusedw[0] <= lpm_fifo0:inst9.wrusedw[0]
wrusedw[1] <= lpm_fifo0:inst9.wrusedw[1]
wrusedw[2] <= lpm_fifo0:inst9.wrusedw[2]
wrusedw[3] <= lpm_fifo0:inst9.wrusedw[3]
wrusedw[4] <= lpm_fifo0:inst9.wrusedw[4]


|429_enc_dec|clk_div:inst1
rst_n => rst_n~0.IN1
clk => cnt[5].CLK
clk => cnt[4].CLK
clk => cnt[3].CLK
clk => cnt[2].CLK
clk => cnt[1].CLK
clk => cnt[0].CLK
clk => clk_in~reg0.CLK
clk => cnt[6].CLK
clk_rate => always0~0.IN0
clk_rate => always0~1.IN1
clk_in <= clk_in~2.DB_MAX_OUTPUT_PORT_TYPE
bclk <= bclk_gen:b1.port2


|429_enc_dec|clk_div:inst1|bclk_gen:b1
rst_n => bcnt[0].ACLR
rst_n => bcnt[1].ACLR
clk_in => bcnt[0].CLK
clk_in => bclk~reg0.CLK
clk_in => bcnt[1].CLK
bclk <= bclk~reg0.DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|word_gap_timer:inst5
null1_data => always0~0.IN0
rst_n => always0~1.IN1
bclk => always0~0.IN1
eos => always0~1.IN0
word_gap <= word_gap~reg0.DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|null1sfr:inst3
clk_in => clk_in~0.IN1
rst_n => null1_sfr[1].ACLR
rst_n => null1_sfr[2].ACLR
rst_n => null1_sfr[3].ACLR
rst_n => null1_sfr[4].ACLR
rst_n => null1_sfr[5].ACLR
rst_n => null1_sfr[6].ACLR
rst_n => null1_sfr[7].ACLR
rst_n => null1_sfr[8].ACLR
rst_n => null1_sfr[9].ACLR
rst_n => null1_sfr[0].ACLR
null1 => null1_sfr[9].DATAIN
null1_data <= R_SY_D_FF1:d3.port3


|429_enc_dec|null1sfr:inst3|R_SY_D_FF1:d3
RB => Q~reg0.ACLR
D => Q~reg0.DATAIN
CLK => Q~reg0.CLK
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|rx_input:inst
rnb => null~0.IN1
rnb => zeros.DATAIN
rna => null~0.IN0
rna => ones.DATAIN
ones <= rna.DB_MAX_OUTPUT_PORT_TYPE
null <= null~0.DB_MAX_OUTPUT_PORT_TYPE
zeros <= rnb.DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|bit_cnt:inst7
rst_n => bit_counter[3].PRESET
rst_n => bit_counter[2].PRESET
rst_n => bit_counter[1].PRESET
rst_n => bit_counter[0].PRESET
rst_n => bit_counter[4].PRESET
bc_crt => bit_clk~0.IN1
bc_crt => comb~0.IN0
clk_in => clk_in~0.IN1
bclk => bclk~0.IN2
eos <= R_SY_D_FF1:d2.port3
bit_clk <= bit_clk~0.DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|bit_cnt:inst7|R_SY_D_FF1:d1
RB => Q~reg0.ACLR
D => Q~reg0.DATAIN
CLK => Q~reg0.CLK
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|bit_cnt:inst7|R_SY_D_FF1:d2
RB => Q~reg0.ACLR
D => Q~reg0.DATAIN
CLK => Q~reg0.CLK
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|seq_ctr:inst6
rst_n => always0~1.IN1
zeros1_data => always0~0.IN0
ones1_data => always0~0.IN1
word_gap => bc_crt~reg0.DATAIN
eos => always0~1.IN0
bc_crt <= bc_crt~reg0.DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|zerossfr:inst4
clk_in => zeros_sfr[1].CLK
clk_in => zeros_sfr[2].CLK
clk_in => zeros_sfr[3].CLK
clk_in => zeros_sfr[4].CLK
clk_in => zeros_sfr[5].CLK
clk_in => zeros_sfr[6].CLK
clk_in => zeros_sfr[7].CLK
clk_in => zeros_sfr[8].CLK
clk_in => zeros_sfr[9].CLK
clk_in => zeros_sfr[0].CLK
rst_n => zeros_sfr[1].ACLR
rst_n => zeros_sfr[2].ACLR
rst_n => zeros_sfr[3].ACLR
rst_n => zeros_sfr[4].ACLR
rst_n => zeros_sfr[5].ACLR
rst_n => zeros_sfr[6].ACLR
rst_n => zeros_sfr[7].ACLR
rst_n => zeros_sfr[8].ACLR
rst_n => zeros_sfr[9].ACLR
rst_n => zeros_sfr[0].ACLR
zeros1 => zeros_sfr[9].DATAIN
zeros1_data <= R_SY_D_FF:d1.port2


|429_enc_dec|zerossfr:inst4|R_SY_D_FF:d1
RB => Q~reg0.ACLR
CLK => Q~reg0.CLK
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|onessfr:inst2
rst_n => ones_sfr[1].ACLR
rst_n => ones_sfr[2].ACLR
rst_n => ones_sfr[3].ACLR
rst_n => ones_sfr[4].ACLR
rst_n => ones_sfr[5].ACLR
rst_n => ones_sfr[6].ACLR
rst_n => ones_sfr[7].ACLR
rst_n => ones_sfr[8].ACLR
rst_n => ones_sfr[9].ACLR
rst_n => ones_sfr[0].ACLR
ones1 => ones_sfr[9].DATAIN
clk_in => ones_sfr[1].CLK
clk_in => ones_sfr[2].CLK
clk_in => ones_sfr[3].CLK
clk_in => ones_sfr[4].CLK
clk_in => ones_sfr[5].CLK
clk_in => ones_sfr[6].CLK
clk_in => ones_sfr[7].CLK
clk_in => ones_sfr[8].CLK
clk_in => ones_sfr[9].CLK
clk_in => ones_sfr[0].CLK
ones1_data <= R_SY_D_FF:d2.port2


|429_enc_dec|onessfr:inst2|R_SY_D_FF:d2
RB => Q~reg0.ACLR
CLK => Q~reg0.CLK
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE


|429_enc_dec|data_sfr:inst8
rst_n => always0~0.IN1
eos => eos~0.IN1
bit_clk => data_out[31].CLK
bit_clk => data_out[30].CLK
bit_clk => data_out[29].CLK
bit_clk => data_out[28].CLK
bit_clk => data_out[27].CLK
bit_clk => data_out[26].CLK
bit_clk => data_out[25].CLK
bit_clk => data_out[24].CLK
bit_clk => data_out[23].CLK
bit_clk => data_out[22].CLK
bit_clk => data_out[21].CLK
bit_clk => data_out[20].CLK
bit_clk => data_out[19].CLK
bit_clk => data_out[18].CLK
bit_clk => data_out[17].CLK
bit_clk => data_out[16].CLK
bit_clk => data_out[15].CLK
bit_clk => data_out[14].CLK
bit_clk => data_out[13].CLK
bit_clk => data_out[12].CLK
bit_clk => data_out[11].CLK
bit_clk => data_out[10].CLK
bit_clk => data_out[9].CLK
bit_clk => data_out[8].CLK
bit_clk => data_out[7].CLK
bit_clk => data_out[6].CLK
bit_clk => data_out[5].CLK
bit_clk => data_out[4].CLK
bit_clk => data_out[3].CLK
bit_clk => data_out[2].CLK
bit_clk => data_out[1].CLK
bit_clk => data_out[0].CLK
bit_clk => par_chec~reg0.CLK
ones1_data => add~0.IN1
ones1_data => data_out~31.DATAA
par_chec <= par_chec~0.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= data_lath:data_lath1.port3
data[1] <= data_lath:data_lath1.port3
data[2] <= data_lath:data_lath1.port3
data[3] <= data_lath:data_lath1.port3
data[4] <= data_lath:data_lath1.port3
data[5] <= data_lath:data_lath1.port3
data[6] <= data_lath:data_lath1.port3
data[7] <= data_lath:data_lath1.port3
data[8] <= data_lath:data_lath1.port3
data[9] <= data_lath:data_lath1.port3
data[10] <= data_lath:data_lath1.port3
data[11] <= data_lath:data_lath1.port3
data[12] <= data_lath:data_lath1.port3
data[13] <= data_lath:data_lath1.port3
data[14] <= data_lath:data_lath1.port3
data[15] <= data_lath:data_lath1.port3
data[16] <= data_lath:data_lath1.port3
data[17] <= data_lath:data_lath1.port3
data[18] <= data_lath:data_lath1.port3
data[19] <= data_lath:data_lath1.port3
data[20] <= data_lath:data_lath1.port3
data[21] <= data_lath:data_lath1.port3
data[22] <= data_lath:data_lath1.port3
data[23] <= data_lath:data_lath1.port3
data[24] <= data_lath:data_lath1.port3
data[25] <= data_lath:data_lath1.port3
data[26] <= data_lath:data_lath1.port3
data[27] <= data_lath:data_lath1.port3
data[28] <= data_lath:data_lath1.port3
data[29] <= data_lath:data_lath1.port3
data[30] <= data_lath:data_lath1.port3
data[31] <= data_lath:data_lath1.port3


|429_enc_dec|data_sfr:inst8|data_lath:data_lath1
eos => data[30]~reg0.CLK
eos => data[29]~reg0.CLK
eos => data[28]~reg0.CLK
eos => data[27]~reg0.CLK
eos => data[26]~reg0.CLK
eos => data[25]~reg0.CLK
eos => data[24]~reg0.CLK
eos => data[23]~reg0.CLK
eos => data[22]~reg0.CLK
eos => data[21]~reg0.CLK
eos => data[20]~reg0.CLK
eos => data[19]~reg0.CLK
eos => data[18]~reg0.CLK
eos => data[17]~reg0.CLK
eos => data[16]~reg0.CLK
eos => data[15]~reg0.CLK
eos => data[14]~reg0.CLK
eos => data[13]~reg0.CLK