dcfifo_vos.tdf

Quartus开发环境下开发的Arinc 429总线收发器工程

--dcfifo CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=32 LPM_SHOWAHEAD="OFF" LPM_WIDTH=32 LPM_WIDTHU=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" data q rdclk rdempty rdreq wrclk wrfull wrreq wrusedw
--VERSION_BEGIN 4.1 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:03:05:02:46:42:SJ cbx_altdpram 2004:05:14:13:10:08:SJ cbx_altsyncram 2004:06:23:18:19:30:SJ cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_dcfifo 2004:06:03:11:08:42:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compare 2004:04:12:17:30:12:SJ cbx_lpm_counter 2004:04:21:01:21:20:SJ cbx_lpm_decode 2004:03:10:10:44:06:SJ cbx_lpm_mux 2004:03:10:10:50:34:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_scfifo 2004:06:03:11:12:32:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ cbx_util 2004:03:29:17:03:30:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
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--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.


FUNCTION a_gray2bin_8cb (gray[4..0])
RETURNS ( bin[4..0]);
FUNCTION a_graycounter_aq5 (clock, cnt_en)
RETURNS ( q[4..0]);
FUNCTION a_graycounter_5j6 (clock, cnt_en)
RETURNS ( q[4..0]);
FUNCTION altsyncram_2hp (address_a[4..0], address_b[4..0], addressstall_b, clock0, clock1, clocken1, data_a[31..0], wren_a)
RETURNS ( q_b[31..0]);
FUNCTION alt_synch_pipe_h62 (clock, d[4..0])
RETURNS ( q[4..0]);
FUNCTION dffpipe_er2 (clock, d[4..0])
RETURNS ( q[4..0]);
FUNCTION add_sub_u5c (dataa[4..0], datab[4..0])
RETURNS ( result[4..0]);

--synthesis_resources = cycloneii_lcell_comb 5 lut 46 ram_bits (auto) 1024 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{-to p0addr} POWER_UP_LEVEL=LOW";

SUBDESIGN dcfifo_vos
( 
	data[31..0]	:	input;
	q[31..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdreq	:	input;
	wrclk	:	input;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[4..0]	:	output;
) 
VARIABLE 
	wrptr_g_gray2bin : a_gray2bin_8cb;
	ws_dgrp_gray2bin : a_gray2bin_8cb;
	rdptr_g1p : a_graycounter_aq5;
	wrptr_g1p : a_graycounter_5j6;
	fifo_ram : altsyncram_2hp;
	delayed_wrptr_g[4..0] : dffe;
	p0addr : dffe
		WITH (
			POWER_UP_HIGH = "OFF"
		);
	rdptr_g[4..0] : dffe;
	wrptr_g[4..0] : dffe;
	rs_dgwp : alt_synch_pipe_h62;
	ws_brp : dffpipe_er2;
	ws_bwp : dffpipe_er2;
	ws_dgrp : alt_synch_pipe_h62;
	wrusedw_sub : add_sub_u5c;
	rdempty_eq_comp_aeb_int	:	WIRE;
	rdempty_eq_comp_aeb	:	WIRE;
	rdempty_eq_comp_dataa[4..0]	:	WIRE;
	rdempty_eq_comp_datab[4..0]	:	WIRE;
	wrfull_eq_comp_aeb_int	:	WIRE;
	wrfull_eq_comp_aeb	:	WIRE;
	wrfull_eq_comp_dataa[4..0]	:	WIRE;
	wrfull_eq_comp_datab[4..0]	:	WIRE;
	int_rdempty	: WIRE;
	int_wrfull	: WIRE;
	rdcnt_addr_ena	: WIRE;
	valid_rdreq	: WIRE;
	valid_wrreq	: WIRE;

BEGIN 
	wrptr_g_gray2bin.gray[] = wrptr_g[].Q;
	ws_dgrp_gray2bin.gray[] = ws_dgrp.q[];
	rdptr_g1p.clock = rdclk;
	rdptr_g1p.cnt_en = rdcnt_addr_ena;
	wrptr_g1p.clock = wrclk;
	wrptr_g1p.cnt_en = valid_wrreq;
	fifo_ram.address_a[] = wrptr_g[].Q;
	fifo_ram.address_b[] = rdptr_g1p.q[];
	fifo_ram.addressstall_b = (! rdcnt_addr_ena);
	fifo_ram.clock0 = wrclk;
	fifo_ram.clock1 = rdclk;
	fifo_ram.clocken1 = valid_rdreq;
	fifo_ram.data_a[] = data[];
	fifo_ram.wren_a = valid_wrreq;
	delayed_wrptr_g[].CLK = wrclk;
	delayed_wrptr_g[].D = wrptr_g[].Q;
	p0addr.CLK = rdclk;
	p0addr.D = B"1";
	rdptr_g[].CLK = rdclk;
	rdptr_g[].D = rdptr_g1p.q[];
	rdptr_g[].ENA = valid_rdreq;
	wrptr_g[].CLK = wrclk;
	wrptr_g[].D = wrptr_g1p.q[];
	wrptr_g[].ENA = valid_wrreq;
	rs_dgwp.clock = rdclk;
	rs_dgwp.d[] = delayed_wrptr_g[].Q;
	ws_brp.clock = wrclk;
	ws_brp.d[] = ws_dgrp_gray2bin.bin[];
	ws_bwp.clock = wrclk;
	ws_bwp.d[] = wrptr_g_gray2bin.bin[];
	ws_dgrp.clock = wrclk;
	ws_dgrp.d[] = rdptr_g[].Q;
	wrusedw_sub.dataa[] = ws_bwp.q[];
	wrusedw_sub.datab[] = ws_brp.q[];
	IF (rdempty_eq_comp_dataa[] == rdempty_eq_comp_datab[]) THEN
		rdempty_eq_comp_aeb_int = VCC;
	ELSE
		rdempty_eq_comp_aeb_int = GND;
	END IF;
	rdempty_eq_comp_aeb = rdempty_eq_comp_aeb_int;
	rdempty_eq_comp_dataa[] = rs_dgwp.q[];
	rdempty_eq_comp_datab[] = rdptr_g[].Q;
	IF (wrfull_eq_comp_dataa[] == wrfull_eq_comp_datab[]) THEN
		wrfull_eq_comp_aeb_int = VCC;
	ELSE
		wrfull_eq_comp_aeb_int = GND;
	END IF;
	wrfull_eq_comp_aeb = wrfull_eq_comp_aeb_int;
	wrfull_eq_comp_dataa[] = ws_dgrp.q[];
	wrfull_eq_comp_datab[] = wrptr_g1p.q[];
	int_rdempty = rdempty_eq_comp_aeb;
	int_wrfull = wrfull_eq_comp_aeb;
	q[] = fifo_ram.q_b[];
	rdcnt_addr_ena = (valid_rdreq # (! p0addr.Q));
	rdempty = int_rdempty;
	valid_rdreq = (rdreq & (! int_rdempty));
	valid_wrreq = (wrreq & (! int_wrfull));
	wrfull = int_wrfull;
	wrusedw[] = wrusedw_sub.result[];
END;
--VALID FILE