429_enc_dec.tan.qmsg

Quartus开发环境下开发的Arinc 429总线收发器工程

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "27 " "Warning: Found 27 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "inst11 " "Info: Detected gated clock inst11 as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/429_enc_dec.bdf" "" "" { Schematic "E:/王云山资料/fpga/429_enc_dec/429_enc_dec.bdf" { { 960 432 496 1008 "inst11" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "inst11" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "onessfr:inst2\|ones_sfr\[5\] " "Info: Detected ripple clock onessfr:inst2\|ones_sfr\[5\] as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/onessfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/onessfr.v" 48 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "onessfr:inst2\|ones_sfr\[5\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "onessfr:inst2\|ones_sfr\[4\] " "Info: Detected ripple clock onessfr:inst2\|ones_sfr\[4\] as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/onessfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/onessfr.v" 48 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "onessfr:inst2\|ones_sfr\[4\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "onessfr:inst2\|ones_sfr\[6\] " "Info: Detected ripple clock onessfr:inst2\|ones_sfr\[6\] as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/onessfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/onessfr.v" 48 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "onessfr:inst2\|ones_sfr\[6\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "zerossfr:inst4\|zeros_sfr\[6\] " "Info: Detected ripple clock zerossfr:inst4\|zeros_sfr\[6\] as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "zerossfr:inst4\|zeros_sfr\[6\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "zerossfr:inst4\|zeros_sfr\[4\] " "Info: Detected ripple clock zerossfr:inst4\|zeros_sfr\[4\] as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "zerossfr:inst4\|zeros_sfr\[4\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "zerossfr:inst4\|zeros_sfr\[5\] " "Info: Detected ripple clock zerossfr:inst4\|zeros_sfr\[5\] as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "zerossfr:inst4\|zeros_sfr\[5\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "onessfr:inst2\|ones1_nval~46 " "Info: Detected gated clock onessfr:inst2\|ones1_nval~46 as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/onessfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/onessfr.v" 46 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "onessfr:inst2\|ones1_nval~46" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "onessfr:inst2\|ones_sfr\[0\] " "Info: Detected ripple clock onessfr:inst2\|ones_sfr\[0\] as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/onessfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/onessfr.v" 48 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "onessfr:inst2\|ones_sfr\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "onessfr:inst2\|ones_sfr\[2\] " "Info: Detected ripple clock onessfr:inst2\|ones_sfr\[2\] as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/onessfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/onessfr.v" 48 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "onessfr:inst2\|ones_sfr\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "onessfr:inst2\|ones_sfr\[1\] " "Info: Detected ripple clock onessfr:inst2\|ones_sfr\[1\] as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/onessfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/onessfr.v" 48 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "onessfr:inst2\|ones_sfr\[1\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "zerossfr:inst4\|zeros1_nval~46 " "Info: Detected gated clock zerossfr:inst4\|zeros1_nval~46 as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" 48 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "zerossfr:inst4\|zeros1_nval~46" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "zerossfr:inst4\|zeros_sfr\[1\] " "Info: Detected ripple clock zerossfr:inst4\|zeros_sfr\[1\] as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "zerossfr:inst4\|zeros_sfr\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "zerossfr:inst4\|zeros_sfr\[0\] " "Info: Detected ripple clock zerossfr:inst4\|zeros_sfr\[0\] as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "zerossfr:inst4\|zeros_sfr\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "zerossfr:inst4\|zeros_sfr\[2\] " "Info: Detected ripple clock zerossfr:inst4\|zeros_sfr\[2\] as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "zerossfr:inst4\|zeros_sfr\[2\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "onessfr:inst2\|ones1_val " "Info: Detected gated clock onessfr:inst2\|ones1_val as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/onessfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/onessfr.v" 45 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "onessfr:inst2\|ones1_val" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "zerossfr:inst4\|zeros1_val " "Info: Detected gated clock zerossfr:inst4\|zeros1_val as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" 47 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "zerossfr:inst4\|zeros1_val" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "onessfr:inst2\|R_SY_D_FF:d2\|Q " "Info: Detected ripple clock onessfr:inst2\|R_SY_D_FF:d2\|Q as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/R_SY_D_FF.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/R_SY_D_FF.v" 3 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "onessfr:inst2\|R_SY_D_FF:d2\|Q" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "zerossfr:inst4\|R_SY_D_FF:d1\|Q " "Info: Detected ripple clock zerossfr:inst4\|R_SY_D_FF:d1\|Q as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/R_SY_D_FF.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/R_SY_D_FF.v" 3 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "zerossfr:inst4\|R_SY_D_FF:d1\|Q" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "seq_ctr:inst6\|always0~0 " "Info: Detected gated clock seq_ctr:inst6\|always0~0 as buffer" {  } { { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "seq_ctr:inst6\|always0~0" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "bit_cnt:inst7\|bit_clk " "Info: Detected gated clock bit_cnt:inst7\|bit_clk as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" 45 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "bit_cnt:inst7\|bit_clk" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "seq_ctr:inst6\|bc_crt " "Info: Detected ripple clock seq_ctr:inst6\|bc_crt as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/seq_ctr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/seq_ctr.v" 45 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "seq_ctr:inst6\|bc_crt" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "null1sfr:inst3\|R_SY_D_FF1:d3\|Q " "Info: Detected ripple clock null1sfr:inst3\|R_SY_D_FF1:d3\|Q as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" 71 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "null1sfr:inst3\|R_SY_D_FF1:d3\|Q" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div:inst1\|bclk_gen:b1\|bclk " "Info: Detected ripple clock clk_div:inst1\|bclk_gen:b1\|bclk as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/clk_div.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/clk_div.v" 74 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "clk_div:inst1\|bclk_gen:b1\|bclk" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "bit_cnt:inst7\|R_SY_D_FF1:d2\|Q " "Info: Detected ripple clock bit_cnt:inst7\|R_SY_D_FF1:d2\|Q as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" 71 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "bit_cnt:inst7\|R_SY_D_FF1:d2\|Q" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "word_gap_timer:inst5\|always0~0 " "Info: Detected gated clock word_gap_timer:inst5\|always0~0 as buffer" {  } { { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "word_gap_timer:inst5\|always0~0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div:inst1\|clk_in " "Info: Detected ripple clock clk_div:inst1\|clk_in as buffer" {  } { { "E:/王云山资料/fpga/429_enc_dec/clk_div.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/clk_div.v" 42 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "clk_div:inst1\|clk_in" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[1\] register bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[4\] 111.459 ns " "Info: Slack time is 111.459 ns for clock clk between source register bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[1\] and destination register bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[4\]" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "73.85 MHz 13.541 ns " "Info: Fmax is 73.85 MHz (period= 13.541 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "119.581 ns + Largest register register " "Info: + Largest register to register requirement is 119.581 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "125.000 ns + " "Info: + Setup relationship between source and destination is 125.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 125.000 ns " "Info: + Latch edge is 125.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 125.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock clk is 125.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 125.000 ns 0.000 ns  50 " "Info: Clock period of Source clock clk is 125.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.141 ns + Largest " "Info: + Largest clock skew is -5.141 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.517 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 10.517 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.355 ns) 1.355 ns clk 1 CLK IOC_X0_Y6_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.355 ns) = 1.355 ns; Loc. = IOC_X0_Y6_N1; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/429_enc_dec.bdf" "" "" { Schematic "E:/王云山资料/fpga/429_enc_dec/429_enc_dec.bdf" { { 192 -96 72 208 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.176 ns) + CELL(0.000 ns) 1.531 ns clk~clkctrl 2 COMB CLKCTRL_G1 8 " "Info: 2: + IC(0.176 ns) + CELL(0.000 ns) = 1.531 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "0.176 ns" { clk clk~clkctrl } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/429_enc_dec.bdf" "" "" { Schematic "E:/王云山资料/fpga/429_enc_dec/429_enc_dec.bdf" { { 192 -96 72 208 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.928 ns) 3.304 ns clk_div:inst1\|clk_in 3 REG LCFF_X27_Y5_N15 4 " "Info: 3: + IC(0.845 ns) + CELL(0.928 ns) = 3.304 ns; Loc. = LCFF_X27_Y5_N15; Fanout = 4; REG Node = 'clk_div:inst1\|clk_in'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "1.773 ns" { clk~clkctrl clk_div:inst1|clk_in } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/clk_div.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/clk_div.v" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.000 ns) 4.499 ns clk_div:inst1\|clk_in~clkctrl 4 COMB CLKCTRL_G7 34 " "Info: 4: + IC(1.195 ns) + CELL(0.000 ns) = 4.499 ns; Loc. = CLKCTRL_G7; Fanout = 34; COMB Node = 'clk_div:inst1\|clk_in~clkctrl'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "1.195 ns" { clk_div:inst1|clk_in clk_div:inst1|clk_in~clkctrl } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/clk_div.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/clk_div.v" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.810 ns) + CELL(0.928 ns) 6.237 ns clk_div:inst1\|bclk_gen:b1\|bclk 5 REG LCFF_X25_Y7_N13 4 " "Info: 5: + IC(0.810 ns) + CELL(0.928 ns) = 6.237 ns; Loc. = LCFF_X25_Y7_N13; Fanout = 4; REG Node = 'clk_div:inst1\|bclk_gen:b1\|bclk'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "1.738 ns" { clk_div:inst1|clk_in~clkctrl clk_div:inst1|bclk_gen:b1|bclk } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/clk_div.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/clk_div.v" 74 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.079 ns) 6.582 ns bit_cnt:inst7\|bit_clk 6 COMB LCCOMB_X25_Y7_N24 2 " "Info: 6: + IC(0.266 ns) + CELL(0.079 ns) = 6.582 ns; Loc. = LCCOMB_X25_Y7_N24; Fanout = 2; COMB Node = 'bit_cnt:inst7\|bit_clk'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "0.345 ns" { clk_div:inst1|bclk_gen:b1|bclk bit_cnt:inst7|bit_clk } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.340 ns) + CELL(0.000 ns) 8.922 ns bit_cnt:inst7\|bit_clk~clkctrl 7 COMB CLKCTRL_G3 38 " "Info: 7: + IC(2.340 ns) + CELL(0.000 ns) = 8.922 ns; Loc. = CLKCTRL_G3; Fanout = 38; COMB Node = 'bit_cnt:inst7\|bit_clk~clkctrl'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "2.340 ns" { bit_cnt:inst7|bit_clk bit_cnt:inst7|bit_clk~clkctrl } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.810 ns) + CELL(0.785 ns) 10.517 ns bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[4\] 8 REG LCFF_X27_Y8_N29 2 " "Info: 8: + IC(0.810 ns) + CELL(0.785 ns) = 10.517 ns; Loc. = LCFF_X27_Y8_N29; Fanout = 2; REG Node = 'bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[4\]'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "1.595 ns" { bit_cnt:inst7|bit_clk~clkctrl bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4] } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" 73 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.075 ns 38.75 % " "Info: Total cell delay = 4.075 ns ( 38.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.442 ns 61.25 % " "Info: Total interconnect delay = 6.442 ns ( 61.25 % )" {  } {  } 0}  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "10.517 ns" { clk clk~clkctrl clk_div:inst1|clk_in clk_div:inst1|clk_in~clkctrl clk_div:inst1|bclk_gen:b1|bclk bit_cnt:inst7|bit_clk bit_cnt:inst7|bit_clk~clkctrl bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 15.658 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 15.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.355 ns) 1.355 ns clk 1 CLK IOC_X0_Y6_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.355 ns) = 1.355 ns; Loc. = IOC_X0_Y6_N1; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/429_enc_dec.bdf" "" "" { Schematic "E:/王云山资料/fpga/429_enc_dec/429_enc_dec.bdf" { { 192 -96 72 208 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.176 ns) + CELL(0.000 ns) 1.531 ns clk~clkctrl 2 COMB CLKCTRL_G1 8 " "Info: 2: + IC(0.176 ns) + CELL(0.000 ns) = 1.531 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "0.176 ns" { clk clk~clkctrl } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/429_enc_dec.bdf" "" "" { Schematic "E:/王云山资料/fpga/429_enc_dec/429_enc_dec.bdf" { { 192 -96 72 208 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.928 ns) 3.304 ns clk_div:inst1\|clk_in 3 REG LCFF_X27_Y5_N15 4 " "Info: 3: + IC(0.845 ns) + CELL(0.928 ns) = 3.304 ns; Loc. = LCFF_X27_Y5_N15; Fanout = 4; REG Node = 'clk_div:inst1\|clk_in'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "1.773 ns" { clk~clkctrl clk_div:inst1|clk_in } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/clk_div.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/clk_div.v" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.000 ns) 4.499 ns clk_div:inst1\|clk_in~clkctrl 4 COMB CLKCTRL_G7 34 " "Info: 4: + IC(1.195 ns) + CELL(0.000 ns) = 4.499 ns; Loc. = CLKCTRL_G7; Fanout = 34; COMB Node = 'clk_div:inst1\|clk_in~clkctrl'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "1.195 ns" { clk_div:inst1|clk_in clk_div:inst1|clk_in~clkctrl } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/clk_div.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/clk_div.v" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.810 ns) + CELL(0.928 ns) 6.237 ns zerossfr:inst4\|zeros_sfr\[5\] 5 REG LCFF_X24_Y9_N11 2 " "Info: 5: + IC(0.810 ns) + CELL(0.928 ns) = 6.237 ns; Loc. = LCFF_X24_Y9_N11; Fanout = 2; REG Node = 'zerossfr:inst4\|zeros_sfr\[5\]'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "1.738 ns" { clk_div:inst1|clk_in~clkctrl zerossfr:inst4|zeros_sfr[5] } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" 51 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.270 ns) + CELL(0.553 ns) 7.060 ns zerossfr:inst4\|zeros1_nval~46 6 COMB LCCOMB_X24_Y9_N26 2 " "Info: 6: + IC(0.270 ns) + CELL(0.553 ns) = 7.060 ns; Loc. = LCCOMB_X24_Y9_N26; Fanout = 2; COMB Node = 'zerossfr:inst4\|zeros1_nval~46'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "0.823 ns" { zerossfr:inst4|zeros_sfr[5] zerossfr:inst4|zeros1_nval~46 } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.079 ns) 7.424 ns zerossfr:inst4\|zeros1_val 7 COMB LCCOMB_X24_Y9_N16 1 " "Info: 7: + IC(0.285 ns) + CELL(0.079 ns) = 7.424 ns; Loc. = LCCOMB_X24_Y9_N16; Fanout = 1; COMB Node = 'zerossfr:inst4\|zeros1_val'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "0.364 ns" { zerossfr:inst4|zeros1_nval~46 zerossfr:inst4|zeros1_val } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.928 ns) 9.389 ns zerossfr:inst4\|R_SY_D_FF:d1\|Q 8 REG LCFF_X24_Y7_N19 1 " "Info: 8: + IC(1.037 ns) + CELL(0.928 ns) = 9.389 ns; Loc. = LCFF_X24_Y7_N19; Fanout = 1; REG Node = 'zerossfr:inst4\|R_SY_D_FF:d1\|Q'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "1.965 ns" { zerossfr:inst4|zeros1_val zerossfr:inst4|R_SY_D_FF:d1|Q } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/R_SY_D_FF.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/R_SY_D_FF.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.486 ns) + CELL(0.231 ns) 10.106 ns seq_ctr:inst6\|always0~0 9 COMB LCCOMB_X25_Y7_N8 1 " "Info: 9: + IC(0.486 ns) + CELL(0.231 ns) = 10.106 ns; Loc. = LCCOMB_X25_Y7_N8; Fanout = 1; COMB Node = 'seq_ctr:inst6\|always0~0'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "0.717 ns" { zerossfr:inst4|R_SY_D_FF:d1|Q seq_ctr:inst6|always0~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.329 ns) + CELL(0.928 ns) 11.363 ns seq_ctr:inst6\|bc_crt 10 REG LCFF_X25_Y7_N25 2 " "Info: 10: + IC(0.329 ns) + CELL(0.928 ns) = 11.363 ns; Loc. = LCFF_X25_Y7_N25; Fanout = 2; REG Node = 'seq_ctr:inst6\|bc_crt'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "1.257 ns" { seq_ctr:inst6|always0~0 seq_ctr:inst6|bc_crt } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/seq_ctr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/seq_ctr.v" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.360 ns) 11.723 ns bit_cnt:inst7\|bit_clk 11 COMB LCCOMB_X25_Y7_N24 2 " "Info: 11: + IC(0.000 ns) + CELL(0.360 ns) = 11.723 ns; Loc. = LCCOMB_X25_Y7_N24; Fanout = 2; COMB Node = 'bit_cnt:inst7\|bit_clk'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "0.360 ns" { seq_ctr:inst6|bc_crt bit_cnt:inst7|bit_clk } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.340 ns) + CELL(0.000 ns) 14.063 ns bit_cnt:inst7\|bit_clk~clkctrl 12 COMB CLKCTRL_G3 38 " "Info: 12: + IC(2.340 ns) + CELL(0.000 ns) = 14.063 ns; Loc. = CLKCTRL_G3; Fanout = 38; COMB Node = 'bit_cnt:inst7\|bit_clk~clkctrl'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "2.340 ns" { bit_cnt:inst7|bit_clk bit_cnt:inst7|bit_clk~clkctrl } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.810 ns) + CELL(0.785 ns) 15.658 ns bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[1\] 13 REG LCFF_X27_Y8_N23 3 " "Info: 13: + IC(0.810 ns) + CELL(0.785 ns) = 15.658 ns; Loc. = LCFF_X27_Y8_N23; Fanout = 3; REG Node = 'bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[1\]'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "1.595 ns" { bit_cnt:inst7|bit_clk~clkctrl bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[1] } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" 73 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.075 ns 45.18 % " "Info: Total cell delay = 7.075 ns ( 45.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.583 ns 54.82 % " "Info: Total interconnect delay = 8.583 ns ( 54.82 % )" {  } {  } 0}  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "15.658 ns" { clk clk~clkctrl clk_div:inst1|clk_in clk_div:inst1|clk_in~clkctrl zerossfr:inst4|zeros_sfr[5] zerossfr:inst4|zeros1_nval~46 zerossfr:inst4|zeros1_val zerossfr:inst4|R_SY_D_FF:d1|Q seq_ctr:inst6|always0~0 seq_ctr:inst6|bc_crt bit_cnt:inst7|bit_clk bit_cnt:inst7|bit_clk~clkctrl bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[1] } "NODE_NAME" } } }  } 0}  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "10.517 ns" { clk clk~clkctrl clk_div:inst1|clk_in clk_div:inst1|clk_in~clkctrl clk_div:inst1|bclk_gen:b1|bclk bit_cnt:inst7|bit_clk bit_cnt:inst7|bit_clk~clkctrl bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4] } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "15.658 ns" { clk clk~clkctrl clk_div:inst1|clk_in clk_div:inst1|clk_in~clkctrl zerossfr:inst4|zeros_sfr[5] zerossfr:inst4|zeros1_nval~46 zerossfr:inst4|zeros1_val zerossfr:inst4|R_SY_D_FF:d1|Q seq_ctr:inst6|always0~0 seq_ctr:inst6|bc_crt bit_cnt:inst7|bit_clk bit_cnt:inst7|bit_clk~clkctrl bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.143 ns - " "Info: - Micro clock to output delay of source is 0.143 ns" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" 73 12 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.135 ns - " "Info: - Micro setup delay of destination is 0.135 ns" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" 73 12 0 } }  } 0}  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "10.517 ns" { clk clk~clkctrl clk_div:inst1|clk_in clk_div:inst1|clk_in~clkctrl clk_div:inst1|bclk_gen:b1|bclk bit_cnt:inst7|bit_clk bit_cnt:inst7|bit_clk~clkctrl bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4] } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "15.658 ns" { clk clk~clkctrl clk_div:inst1|clk_in clk_div:inst1|clk_in~clkctrl zerossfr:inst4|zeros_sfr[5] zerossfr:inst4|zeros1_nval~46 zerossfr:inst4|zeros1_val zerossfr:inst4|R_SY_D_FF:d1|Q seq_ctr:inst6|always0~0 seq_ctr:inst6|bc_crt bit_cnt:inst7|bit_clk bit_cnt:inst7|bit_clk~clkctrl bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.122 ns - Longest register register " "Info: - Longest register to register delay is 8.122 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[1\] 1 REG LCFF_X27_Y8_N23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y8_N23; Fanout = 3; REG Node = 'bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[1\]'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "" { bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[1] } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" 73 12 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.341 ns) + CELL(0.793 ns) 4.134 ns bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|counter_comb_bita1~COUT 2 COMB LCCOMB_X27_Y8_N2 2 " "Info: 2: + IC(3.341 ns) + CELL(0.793 ns) = 4.134 ns; Loc. = LCCOMB_X27_Y8_N2; Fanout = 2; COMB Node = 'bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|counter_comb_bita1~COUT'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "4.134 ns" { bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[1] bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita1~COUT } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.053 ns) 4.187 ns bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|counter_comb_bita2~COUT 3 COMB LCCOMB_X27_Y8_N4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.053 ns) = 4.187 ns; Loc. = LCCOMB_X27_Y8_N4; Fanout = 2; COMB Node = 'bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|counter_comb_bita2~COUT'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "0.053 ns" { bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita1~COUT bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita2~COUT } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" 50 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.053 ns) 4.240 ns bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|counter_comb_bita3~COUT 4 COMB LCCOMB_X27_Y8_N6 1 " "Info: 4: + IC(0.000 ns) + CELL(0.053 ns) = 4.240 ns; Loc. = LCCOMB_X27_Y8_N6; Fanout = 1; COMB Node = 'bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|counter_comb_bita3~COUT'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "0.053 ns" { bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita2~COUT bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita3~COUT } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" 55 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.053 ns) 4.293 ns bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|counter_comb_bita4 5 COMB LCCOMB_X27_Y8_N8 1 " "Info: 5: + IC(0.000 ns) + CELL(0.053 ns) = 4.293 ns; Loc. = LCCOMB_X27_Y8_N8; Fanout = 1; COMB Node = 'bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|counter_comb_bita4'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "0.053 ns" { bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita3~COUT bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita4 } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" 60 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.080 ns) + CELL(0.518 ns) 7.891 ns bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[4\]~feeder 6 COMB LCCOMB_X27_Y8_N28 1 " "Info: 6: + IC(3.080 ns) + CELL(0.518 ns) = 7.891 ns; Loc. = LCCOMB_X27_Y8_N28; Fanout = 1; COMB Node = 'bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[4\]~feeder'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "3.598 ns" { bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita4 bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4]~feeder } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" 73 12 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.231 ns) 8.122 ns bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[4\] 7 REG LCFF_X27_Y8_N29 2 " "Info: 7: + IC(0.000 ns) + CELL(0.231 ns) = 8.122 ns; Loc. = LCFF_X27_Y8_N29; Fanout = 2; REG Node = 'bit_cnt:inst7\|lpm_counter:bit_counter_rtl_0\|cntr_vo7:auto_generated\|pre_hazard\[4\]'" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "0.231 ns" { bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4]~feeder bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4] } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" 73 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.701 ns 20.94 % " "Info: Total cell delay = 1.701 ns ( 20.94 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.421 ns 79.06 % " "Info: Total interconnect delay = 6.421 ns ( 79.06 % )" {  } {  } 0}  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "8.122 ns" { bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[1] bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita1~COUT bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita2~COUT bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita3~COUT bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita4 bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4]~feeder bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4] } "NODE_NAME" } } }  } 0}  } { { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "10.517 ns" { clk clk~clkctrl clk_div:inst1|clk_in clk_div:inst1|clk_in~clkctrl clk_div:inst1|bclk_gen:b1|bclk bit_cnt:inst7|bit_clk bit_cnt:inst7|bit_clk~clkctrl bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4] } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "15.658 ns" { clk clk~clkctrl clk_div:inst1|clk_in clk_div:inst1|clk_in~clkctrl zerossfr:inst4|zeros_sfr[5] zerossfr:inst4|zeros1_nval~46 zerossfr:inst4|zeros1_val zerossfr:inst4|R_SY_D_FF:d1|Q seq_ctr:inst6|always0~0 seq_ctr:inst6|bc_crt bit_cnt:inst7|bit_clk bit_cnt:inst7|bit_clk~clkctrl bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[1] } "NODE_NAME" } } } { "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" "" "" { Report "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec_cmp.qrpt" Compiler "429_enc_dec" "UNKNOWN" "V1" "E:/王云山资料/fpga/429_enc_dec/db/429_enc_dec.quartus_db" { Floorplan "" "" "8.122 ns" { bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[1] bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita1~COUT bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita2~COUT bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita3~COUT bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita4 bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4]~feeder bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4] } "NODE_NAME" } } }  } 0}