altsyncram_2hp.tdf

Quartus开发环境下开发的Arinc 429总线收发器工程

			PORT_A_LAST_ADDRESS = 31,
			PORT_A_LOGICAL_RAM_DEPTH = 32,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 5,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 27,
			PORT_B_LAST_ADDRESS = 31,
			PORT_B_LOGICAL_RAM_DEPTH = 32,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a28 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 5,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 31,
			PORT_A_LOGICAL_RAM_DEPTH = 32,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 5,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 28,
			PORT_B_LAST_ADDRESS = 31,
			PORT_B_LOGICAL_RAM_DEPTH = 32,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a29 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 5,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 31,
			PORT_A_LOGICAL_RAM_DEPTH = 32,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 5,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 29,
			PORT_B_LAST_ADDRESS = 31,
			PORT_B_LOGICAL_RAM_DEPTH = 32,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a30 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 5,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 31,
			PORT_A_LOGICAL_RAM_DEPTH = 32,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 5,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 30,
			PORT_B_LAST_ADDRESS = 31,
			PORT_B_LOGICAL_RAM_DEPTH = 32,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a31 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 5,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 31,
			PORT_A_LOGICAL_RAM_DEPTH = 32,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 5,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 31,
			PORT_B_LAST_ADDRESS = 31,
			PORT_B_LOGICAL_RAM_DEPTH = 32,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	address_a_wire[4..0]	: WIRE;
	address_b_wire[4..0]	: WIRE;

BEGIN 
	ram_block1a[31..0].clk0 = clock0;
	ram_block1a[31..0].clk1 = clock1;
	ram_block1a[31..0].ena1 = clocken1;
	ram_block1a[0].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[1].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[2].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[3].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[4].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[5].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[6].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[7].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[8].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[9].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[10].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[11].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[12].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[13].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[14].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[15].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[16].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[17].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[18].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[19].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[20].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[21].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[22].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[23].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[24].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[25].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[26].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[27].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[28].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[29].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[30].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[31].portaaddr[] = ( B"00000000000", address_a_wire[4..0]);
	ram_block1a[0].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[0..0]);
	ram_block1a[1].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[1..1]);
	ram_block1a[2].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[2..2]);
	ram_block1a[3].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[3..3]);
	ram_block1a[4].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[4..4]);
	ram_block1a[5].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[5..5]);
	ram_block1a[6].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[6..6]);
	ram_block1a[7].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[7..7]);
	ram_block1a[8].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[8..8]);
	ram_block1a[9].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[9..9]);
	ram_block1a[10].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[10..10]);
	ram_block1a[11].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[11..11]);
	ram_block1a[12].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[12..12]);
	ram_block1a[13].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[13..13]);
	ram_block1a[14].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[14..14]);
	ram_block1a[15].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[15..15]);
	ram_block1a[16].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[16..16]);
	ram_block1a[17].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[17..17]);
	ram_block1a[18].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[18..18]);
	ram_block1a[19].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[19..19]);
	ram_block1a[20].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[20..20]);
	ram_block1a[21].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[21..21]);
	ram_block1a[22].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[22..22]);
	ram_block1a[23].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[23..23]);
	ram_block1a[24].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[24..24]);
	ram_block1a[25].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[25..25]);
	ram_block1a[26].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[26..26]);
	ram_block1a[27].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[27..27]);
	ram_block1a[28].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[28..28]);
	ram_block1a[29].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[29..29]);
	ram_block1a[30].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[30..30]);
	ram_block1a[31].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[31..31]);
	ram_block1a[31..0].portawe = wren_a;
	ram_block1a[0].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[1].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[2].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[3].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[4].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[5].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[6].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[7].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[8].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[9].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[10].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[11].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[12].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[13].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[14].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[15].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[16].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[17].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[18].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[19].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[20].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[21].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[22].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[23].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[24].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[25].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[26].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[27].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[28].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[29].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[30].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[31].portbaddr[] = ( B"00000000000", address_b_wire[4..0]);
	ram_block1a[31..0].portbaddrstall = addressstall_b;
	ram_block1a[0].portbrewe = B"1";
	ram_block1a[1].portbrewe = B"1";
	ram_block1a[2].portbrewe = B"1";
	ram_block1a[3].portbrewe = B"1";
	ram_block1a[4].portbrewe = B"1";
	ram_block1a[5].portbrewe = B"1";
	ram_block1a[6].portbrewe = B"1";
	ram_block1a[7].portbrewe = B"1";
	ram_block1a[8].portbrewe = B"1";
	ram_block1a[9].portbrewe = B"1";
	ram_block1a[10].portbrewe = B"1";
	ram_block1a[11].portbrewe = B"1";
	ram_block1a[12].portbrewe = B"1";
	ram_block1a[13].portbrewe = B"1";
	ram_block1a[14].portbrewe = B"1";
	ram_block1a[15].portbrewe = B"1";
	ram_block1a[16].portbrewe = B"1";
	ram_block1a[17].portbrewe = B"1";
	ram_block1a[18].portbrewe = B"1";
	ram_block1a[19].portbrewe = B"1";
	ram_block1a[20].portbrewe = B"1";
	ram_block1a[21].portbrewe = B"1";
	ram_block1a[22].portbrewe = B"1";
	ram_block1a[23].portbrewe = B"1";
	ram_block1a[24].portbrewe = B"1";
	ram_block1a[25].portbrewe = B"1";
	ram_block1a[26].portbrewe = B"1";
	ram_block1a[27].portbrewe = B"1";
	ram_block1a[28].portbrewe = B"1";
	ram_block1a[29].portbrewe = B"1";
	ram_block1a[30].portbrewe = B"1";
	ram_block1a[31].portbrewe = B"1";
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_b[] = ( ram_block1a[31].portbdataout[0..0], ram_block1a[30].portbdataout[0..0], ram_block1a[29].portbdataout[0..0], ram_block1a[28].portbdataout[0..0], ram_block1a[27].portbdataout[0..0], ram_block1a[26].portbdataout[0..0], ram_block1a[25].portbdataout[0..0], ram_block1a[24].portbdataout[0..0], ram_block1a[23].portbdataout[0..0], ram_block1a[22].portbdataout[0..0], ram_block1a[21].portbdataout[0..0], ram_block1a[20].portbdataout[0..0], ram_block1a[19].portbdataout[0..0], ram_block1a[18].portbdataout[0..0], ram_block1a[17].portbdataout[0..0], ram_block1a[16].portbdataout[0..0], ram_block1a[15].portbdataout[0..0], ram_block1a[14].portbdataout[0..0], ram_block1a[13].portbdataout[0..0], ram_block1a[12].portbdataout[0..0], ram_block1a[11].portbdataout[0..0], ram_block1a[10].portbdataout[0..0], ram_block1a[9].portbdataout[0..0], ram_block1a[8].portbdataout[0..0], ram_block1a[7].portbdataout[0..0], ram_block1a[6].portbdataout[0..0], ram_block1a[5].portbdataout[0..0], ram_block1a[4].portbdataout[0..0], ram_block1a[3].portbdataout[0..0], ram_block1a[2].portbdataout[0..0], ram_block1a[1].portbdataout[0..0], ram_block1a[0].portbdataout[0..0]);
END;
--VALID FILE