429_enc_dec.map.qmsg

Quartus开发环境下开发的Arinc 429总线收发器工程

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_aq5.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_aq5.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_aq5 " "Info: Found entity 1: a_graycounter_aq5" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/a_graycounter_aq5.tdf" "a_graycounter_aq5" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/a_graycounter_aq5.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_5j6.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_5j6.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_5j6 " "Info: Found entity 1: a_graycounter_5j6" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/a_graycounter_5j6.tdf" "a_graycounter_5j6" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/a_graycounter_5j6.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_2hp.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_2hp.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_2hp " "Info: Found entity 1: altsyncram_2hp" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/altsyncram_2hp.tdf" "altsyncram_2hp" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/altsyncram_2hp.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_h62.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_h62.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_h62 " "Info: Found entity 1: alt_synch_pipe_h62" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/alt_synch_pipe_h62.tdf" "alt_synch_pipe_h62" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/alt_synch_pipe_h62.tdf" 32 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_h62.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_h62.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_h62 " "Info: Found entity 1: dffpipe_h62" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/dffpipe_h62.tdf" "dffpipe_h62" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/dffpipe_h62.tdf" 30 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_er2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_er2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_er2 " "Info: Found entity 1: dffpipe_er2" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/dffpipe_er2.tdf" "dffpipe_er2" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/dffpipe_er2.tdf" 30 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_u5c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_u5c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_u5c " "Info: Found entity 1: add_sub_u5c" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/add_sub_u5c.tdf" "add_sub_u5c" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/add_sub_u5c.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "lpm_fifo0:inst9\|dcfifo:dcfifo_component\|dcfifo_vos:auto_generated\|dffpipe_er2:ws_bwp\|dffe4a\[4\] lpm_fifo0:inst9\|dcfifo:dcfifo_component\|dcfifo_vos:auto_generated\|delayed_wrptr_g\[4\] " "Info: Duplicate register lpm_fifo0:inst9\|dcfifo:dcfifo_component\|dcfifo_vos:auto_generated\|dffpipe_er2:ws_bwp\|dffe4a\[4\] merged to single register lpm_fifo0:inst9\|dcfifo:dcfifo_component\|dcfifo_vos:auto_generated\|delayed_wrptr_g\[4\]" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/dffpipe_er2.tdf" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/dffpipe_er2.tdf" 37 8 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "bit_cnt:inst7\|bit_counter\[0\]~0 5 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: bit_cnt:inst7\|bit_counter\[0\]~0" {  } { { "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" "" "bit_counter\[0\]~0" { Text "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" 53 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "d:/altera/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "d:/altera/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_vo7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_vo7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_vo7 " "Info: Found entity 1: cntr_vo7" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" "cntr_vo7" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf" 33 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 balanced 46 " "Info: Resynthesizing 0 WYSIWYG logic cells and I/Os using balanced technology mapper which leaves 46 WYSIWYG logic cells and I/Os untouched" {  } {  } 0}
{ "Info" "IOPT_MLS_GATE_LEVEL_RETIMING_STARTED_INFO" "" "Info: Performing gate-level register retiming" {  } {  } 0}
{ "Warning" "WHDB_CLOCK_SETTING_NOT_FOUND" "clk3 " "Warning: Can't find clock settings clk3 in current project -- ignoring clock settings" {  } {  } 0}
{ "Warning" "WHDB_CLOCK_SETTING_NOT_FOUND" "clk3 " "Warning: Can't find clock settings clk3 in current project -- ignoring clock settings" {  } {  } 0}
{ "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_HDR" "110 " "Info: Not allowed to move 110 registers" { { "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_INPUT_DETAILS" "4 " "Info: Not allowed to move 4 registers because they are directly fed by input pins" {  } {  } 0} { "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_OUTPUT_DETAILS" "3 " "Info: Not allowed to move 3 registers because they feed output pins directly" {  } {  } 0} { "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_FED_BY_OTHER_CLOCK_DETAILS" "47 " "Info: Not allowed to move 47 registers because they are fed by registers in a different clock domain" {  } {  } 0} { "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_FEEDING_OTHER_CLOCK_DETAILS" "41 " "Info: Not allowed to move 41 registers because they feed registers in a different clock domain" {  } {  } 0} { "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_FEEDING_SECONDARIES_DETAILS" "15 " "Info: Not allowed to move 15 registers because they feed clock or asynchronous control signals of other registers" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_GATE_LEVEL_RETIMING_RESULTS_HDR" "2 " "Info: Quartus II software applied gate-level register retiming to 2 clock domains" { { "Info" "IOPT_MLS_GATE_LEVEL_RETIMING_RESULTS_DETAILS" "clk_div:inst1\|clk_in 1 1 33 " "Info: Quartus II software applied gate-level register retiming to clock clk_div:inst1\|clk_in: created 1 new registers, removed 1 registers, left 33 registers untouched" {  } {  } 0} { "Info" "IOPT_MLS_GATE_LEVEL_RETIMING_RESULTS_DETAILS" "!inst11 6 8 16 " "Info: Quartus II software applied gate-level register retiming to clock !inst11: created 6 new registers, removed 8 registers, left 16 registers untouched" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "318 " "Info: Implemented 318 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "75 " "Info: Implemented 75 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "205 " "Info: Implemented 205 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "32 " "Info: Implemented 32 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 17 10:43:03 2008 " "Info: Processing ended: Mon Mar 17 10:43:03 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0}  } {  } 0}