429_enc_dec.map.qmsg

Quartus开发环境下开发的Arinc 429总线收发器工程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 17 10:42:52 2008 " "Info: Processing started: Mon Mar 17 10:42:52 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off 429_enc_dec -c 429_enc_dec " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off 429_enc_dec -c 429_enc_dec" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "null1sfr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file null1sfr.v" { { "Info" "ISGN_ENTITY_NAME" "1 null1sfr " "Info: Found entity 1: null1sfr" {  } { { "E:/王云山资料/fpga/429_enc_dec/null1sfr.v" "null1sfr" "" { Text "E:/王云山资料/fpga/429_enc_dec/null1sfr.v" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "429_enc_dec.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 429_enc_dec.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 429_enc_dec " "Info: Found entity 1: 429_enc_dec" {  } { { "E:/王云山资料/fpga/429_enc_dec/429_enc_dec.bdf" "429_enc_dec" "" { Schematic "E:/王云山资料/fpga/429_enc_dec/429_enc_dec.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_input.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rx_input.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_input " "Info: Found entity 1: rx_input" {  } { { "E:/王云山资料/fpga/429_enc_dec/rx_input.v" "rx_input" "" { Text "E:/王云山资料/fpga/429_enc_dec/rx_input.v" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_div.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file clk_div.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_div " "Info: Found entity 1: clk_div" {  } { { "E:/王云山资料/fpga/429_enc_dec/clk_div.v" "clk_div" "" { Text "E:/王云山资料/fpga/429_enc_dec/clk_div.v" 30 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 bclk_gen " "Info: Found entity 2: bclk_gen" {  } { { "E:/王云山资料/fpga/429_enc_dec/clk_div.v" "bclk_gen" "" { Text "E:/王云山资料/fpga/429_enc_dec/clk_div.v" 71 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "zerossfr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file zerossfr.v" { { "Info" "ISGN_ENTITY_NAME" "1 zerossfr " "Info: Found entity 1: zerossfr" {  } { { "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" "zerossfr" "" { Text "E:/王云山资料/fpga/429_enc_dec/zerossfr.v" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "word_gap_timer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file word_gap_timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 word_gap_timer " "Info: Found entity 1: word_gap_timer" {  } { { "E:/王云山资料/fpga/429_enc_dec/word_gap_timer.v" "word_gap_timer" "" { Text "E:/王云山资料/fpga/429_enc_dec/word_gap_timer.v" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seq_ctr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file seq_ctr.v" { { "Info" "ISGN_ENTITY_NAME" "1 seq_ctr " "Info: Found entity 1: seq_ctr" {  } { { "E:/王云山资料/fpga/429_enc_dec/seq_ctr.v" "seq_ctr" "" { Text "E:/王云山资料/fpga/429_enc_dec/seq_ctr.v" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "R_SY_D_FF.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file R_SY_D_FF.v" { { "Info" "ISGN_ENTITY_NAME" "1 R_SY_D_FF " "Info: Found entity 1: R_SY_D_FF" {  } { { "E:/王云山资料/fpga/429_enc_dec/R_SY_D_FF.v" "R_SY_D_FF" "" { Text "E:/王云山资料/fpga/429_enc_dec/R_SY_D_FF.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bit_cnt.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file bit_cnt.v" { { "Info" "ISGN_ENTITY_NAME" "1 bit_cnt " "Info: Found entity 1: bit_cnt" {  } { { "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" "bit_cnt" "" { Text "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" 30 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 R_SY_D_FF1 " "Info: Found entity 2: R_SY_D_FF1" {  } { { "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" "R_SY_D_FF1" "" { Text "E:/王云山资料/fpga/429_enc_dec/bit_cnt.v" 69 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_GENERIC_WARNING_WITH_LOC" "Unconverted VERI-1097: port eos is already declared data_sfr.v(74) " "Warning: Verilog HDL or VHDL warning at data_sfr.v(74): Unconverted VERI-1097: port eos is already declared" {  } { { "E:/王云山资料/fpga/429_enc_dec/data_sfr.v" "" "" { Text "E:/王云山资料/fpga/429_enc_dec/data_sfr.v" 74 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_sfr.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file data_sfr.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_sfr " "Info: Found entity 1: data_sfr" {  } { { "E:/王云山资料/fpga/429_enc_dec/data_sfr.v" "data_sfr" "" { Text "E:/王云山资料/fpga/429_enc_dec/data_sfr.v" 30 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 data_lath " "Info: Found entity 2: data_lath" {  } { { "E:/王云山资料/fpga/429_enc_dec/data_sfr.v" "data_lath" "" { Text "E:/王云山资料/fpga/429_enc_dec/data_sfr.v" 63 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "parity_check.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file parity_check.v" { { "Info" "ISGN_ENTITY_NAME" "1 parity_check " "Info: Found entity 1: parity_check" {  } { { "E:/王云山资料/fpga/429_enc_dec/parity_check.v" "parity_check" "" { Text "E:/王云山资料/fpga/429_enc_dec/parity_check.v" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "onessfr.v 1 1 " "Info: Using design file onessfr.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 onessfr " "Info: Found entity 1: onessfr" {  } { { "E:/王云山资料/fpga/429_enc_dec/onessfr.v" "onessfr" "" { Text "E:/王云山资料/fpga/429_enc_dec/onessfr.v" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "lpm_fifo0.v 1 1 " "Info: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_fifo0 " "Info: Found entity 1: lpm_fifo0" {  } { { "E:/王云山资料/fpga/429_enc_dec/lpm_fifo0.v" "lpm_fifo0" "" { Text "E:/王云山资料/fpga/429_enc_dec/lpm_fifo0.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/libraries/megafunctions/dcfifo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/libraries/megafunctions/dcfifo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo " "Info: Found entity 1: dcfifo" {  } { { "d:/altera/libraries/megafunctions/dcfifo.tdf" "dcfifo" "" { Text "d:/altera/libraries/megafunctions/dcfifo.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dcfifo_vos.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dcfifo_vos.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo_vos " "Info: Found entity 1: dcfifo_vos" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/dcfifo_vos.tdf" "dcfifo_vos" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/dcfifo_vos.tdf" 44 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_gray2bin_8cb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_8cb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_gray2bin_8cb " "Info: Found entity 1: a_gray2bin_8cb" {  } { { "E:/王云山资料/fpga/429_enc_dec/db/a_gray2bin_8cb.tdf" "a_gray2bin_8cb" "" { Text "E:/王云山资料/fpga/429_enc_dec/db/a_gray2bin_8cb.tdf" 28 1 0 } }  } 0}  } {  } 0}