429_enc_dec.cdb.qmsg

Quartus开发环境下开发的Arinc 429总线收发器工程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Compiler Database Interface " "Info: Running Quartus II Compiler Database Interface" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 17 10:43:50 2008 " "Info: Processing started: Mon Mar 17 10:43:50 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb 429_enc_dec -c 429_enc_dec --vqm=E:/王云山资料/fpga/429_enc_dec/atom_netlists/429_enc_dec.vqm " "Info: Command: quartus_cdb 429_enc_dec -c 429_enc_dec --vqm=E:/王云山资料/fpga/429_enc_dec/atom_netlists/429_enc_dec.vqm" {  } {  } 0}
{ "Info" "IBASEO_GENERATE_LOGICLOCK_FILES_FOR_POSTFIT_NETLIST" "" "Info: Generated Verilog Quartus Mapping File using post-fit netlist" {  } {  } 0}
{ "Info" "IQATM_GENERATED_VQM_FILE" "E:/王云山资料/fpga/429_enc_dec/atom_netlists/429_enc_dec.vqm " "Info: Generated Verilog Quartus Mapping File E:/王云山资料/fpga/429_enc_dec/atom_netlists/429_enc_dec.vqm" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Compiler Database Interface 0 s 0 s " "Info: Quartus II Compiler Database Interface was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 17 10:43:51 2008 " "Info: Processing ended: Mon Mar 17 10:43:51 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}