a_graycounter_aq5.tdf

Quartus开发环境下开发的Arinc 429总线收发器工程

--a_graycounter DEVICE_FAMILY="Cyclone II" WIDTH=5 clock cnt_en q
--VERSION_BEGIN 4.1 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:03:05:02:46:42:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ cbx_util 2004:03:29:17:03:30:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.


FUNCTION stratix_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( 	cin_used,	lut_mask,	operation_mode,	output_mode,	register_cascade_mode,	sum_lutc_input,	synch_mode) 
RETURNS ( combout, cout, regout);

--synthesis_resources = lut 6 
SUBDESIGN a_graycounter_aq5
( 
	clock	:	input;
	cnt_en	:	input;
	q[4..0]	:	output;
) 
VARIABLE 
	countera0 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "C6A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera1 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera2 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera3 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6C50",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	countera4 : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A5A",
			operation_mode = "normal",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	parity : stratix_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6682",
			operation_mode = "arithmetic",
			synch_mode = "on"
		);
	power_modified_counter_values[4..0]	: WIRE;
	sclr	: NODE;
	updown	: NODE;

BEGIN 
	countera[0].cin = parity.cout;
	countera[1].cin = countera[0].cout;
	countera[2].cin = countera[1].cout;
	countera[3].cin = countera[2].cout;
	countera[4].cin = countera[3].cout;
	countera[4..0].clk = clock;
	countera[0].dataa = cnt_en;
	countera[1].dataa = power_modified_counter_values[0..0];
	countera[2].dataa = power_modified_counter_values[1..1];
	countera[3].dataa = power_modified_counter_values[2..2];
	countera[4].dataa = power_modified_counter_values[4..4];
	countera[0].datab = countera[0].regout;
	countera[1].datab = power_modified_counter_values[1..1];
	countera[2].datab = power_modified_counter_values[2..2];
	countera[3].datab = power_modified_counter_values[3..3];
	countera[4..0].sclr = sclr;
	parity.cin = updown;
	parity.clk = clock;
	parity.dataa = cnt_en;
	parity.datab = parity.regout;
	parity.sclr = sclr;
	power_modified_counter_values[] = ( countera[4..0].regout);
	q[] = power_modified_counter_values[];
	sclr = GND;
	updown = VCC;
END;
--VALID FILE