null1sfr.v

Quartus开发环境下开发的Arinc 429总线收发器工程

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
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// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
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// Generated by Quartus II Version 4.1 (Build Build 181 06/29/2004)
// Created on Fri Mar 07 11:38:44 2008

//  Module Declaration
module null1sfr
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	clk_in, rst_n, null1, null1_data, eos
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input clk_in;
	input rst_n;
	input null1;
	input eos;
	output null1_data;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
    reg [0:9] null1_sfr;
    wire     null1_val;
   

always @(posedge clk_in or negedge rst_n) begin
   if (!rst_n ) begin   
      null1_sfr <= 10'd0 ;
   end
   else  begin 
     null1_sfr <= {null1_sfr[1:9], null1} ;
   end
 
end

assign null1_val=null1_sfr[0]&& null1_sfr[1]&& null1_sfr[2];

 R_SY_D_FF1 d3(~eos, null1_val, clk_in,  null1_data );
 

endmodule