429_enc_dec.map.eqn

Quartus开发环境下开发的Arinc 429总线收发器工程

--V1_q_b[16] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[16]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[16]_PORT_A_data_in = S1_data[16];
V1_q_b[16]_PORT_A_data_in_reg = DFFE(V1_q_b[16]_PORT_A_data_in, V1_q_b[16]_clock_0, , , );
V1_q_b[16]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[16]_PORT_A_address_reg = DFFE(V1_q_b[16]_PORT_A_address, V1_q_b[16]_clock_0, , , );
V1_q_b[16]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[16]_PORT_B_address_reg = DFFE(V1_q_b[16]_PORT_B_address, V1_q_b[16]_clock_1, , , V1_q_b[16]_clock_enable_1);
V1_q_b[16]_PORT_A_write_enable = U1L02;
V1_q_b[16]_PORT_A_write_enable_reg = DFFE(V1_q_b[16]_PORT_A_write_enable, V1_q_b[16]_clock_0, , , );
V1_q_b[16]_PORT_B_read_enable = VCC;
V1_q_b[16]_PORT_B_read_enable_reg = DFFE(V1_q_b[16]_PORT_B_read_enable, V1_q_b[16]_clock_1, , , V1_q_b[16]_clock_enable_1);
V1_q_b[16]_clock_0 = inst11;
V1_q_b[16]_clock_1 = rdclk;
V1_q_b[16]_clock_enable_1 = U1L71;
V1_q_b[16]_PORT_B_data_out = MEMORY(V1_q_b[16]_PORT_A_data_in_reg, , V1_q_b[16]_PORT_A_address_reg, V1_q_b[16]_PORT_B_address_reg, V1_q_b[16]_PORT_A_write_enable_reg, V1_q_b[16]_PORT_B_read_enable_reg, , , V1_q_b[16]_clock_0, V1_q_b[16]_clock_1, , V1_q_b[16]_clock_enable_1, , );
V1_q_b[16]_PORT_B_data_out_reg = DFFE(V1_q_b[16]_PORT_B_data_out, V1_q_b[16]_clock_1, , , V1_q_b[16]_clock_enable_1);
V1_q_b[16] = V1_q_b[16]_PORT_B_data_out_reg[0];


--V1_q_b[15] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[15]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[15]_PORT_A_data_in = S1_data[15];
V1_q_b[15]_PORT_A_data_in_reg = DFFE(V1_q_b[15]_PORT_A_data_in, V1_q_b[15]_clock_0, , , );
V1_q_b[15]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[15]_PORT_A_address_reg = DFFE(V1_q_b[15]_PORT_A_address, V1_q_b[15]_clock_0, , , );
V1_q_b[15]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[15]_PORT_B_address_reg = DFFE(V1_q_b[15]_PORT_B_address, V1_q_b[15]_clock_1, , , V1_q_b[15]_clock_enable_1);
V1_q_b[15]_PORT_A_write_enable = U1L02;
V1_q_b[15]_PORT_A_write_enable_reg = DFFE(V1_q_b[15]_PORT_A_write_enable, V1_q_b[15]_clock_0, , , );
V1_q_b[15]_PORT_B_read_enable = VCC;
V1_q_b[15]_PORT_B_read_enable_reg = DFFE(V1_q_b[15]_PORT_B_read_enable, V1_q_b[15]_clock_1, , , V1_q_b[15]_clock_enable_1);
V1_q_b[15]_clock_0 = inst11;
V1_q_b[15]_clock_1 = rdclk;
V1_q_b[15]_clock_enable_1 = U1L71;
V1_q_b[15]_PORT_B_data_out = MEMORY(V1_q_b[15]_PORT_A_data_in_reg, , V1_q_b[15]_PORT_A_address_reg, V1_q_b[15]_PORT_B_address_reg, V1_q_b[15]_PORT_A_write_enable_reg, V1_q_b[15]_PORT_B_read_enable_reg, , , V1_q_b[15]_clock_0, V1_q_b[15]_clock_1, , V1_q_b[15]_clock_enable_1, , );
V1_q_b[15]_PORT_B_data_out_reg = DFFE(V1_q_b[15]_PORT_B_data_out, V1_q_b[15]_clock_1, , , V1_q_b[15]_clock_enable_1);
V1_q_b[15] = V1_q_b[15]_PORT_B_data_out_reg[0];


--V1_q_b[14] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[14]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[14]_PORT_A_data_in = S1_data[14];
V1_q_b[14]_PORT_A_data_in_reg = DFFE(V1_q_b[14]_PORT_A_data_in, V1_q_b[14]_clock_0, , , );
V1_q_b[14]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[14]_PORT_A_address_reg = DFFE(V1_q_b[14]_PORT_A_address, V1_q_b[14]_clock_0, , , );
V1_q_b[14]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[14]_PORT_B_address_reg = DFFE(V1_q_b[14]_PORT_B_address, V1_q_b[14]_clock_1, , , V1_q_b[14]_clock_enable_1);
V1_q_b[14]_PORT_A_write_enable = U1L02;
V1_q_b[14]_PORT_A_write_enable_reg = DFFE(V1_q_b[14]_PORT_A_write_enable, V1_q_b[14]_clock_0, , , );
V1_q_b[14]_PORT_B_read_enable = VCC;
V1_q_b[14]_PORT_B_read_enable_reg = DFFE(V1_q_b[14]_PORT_B_read_enable, V1_q_b[14]_clock_1, , , V1_q_b[14]_clock_enable_1);
V1_q_b[14]_clock_0 = inst11;
V1_q_b[14]_clock_1 = rdclk;
V1_q_b[14]_clock_enable_1 = U1L71;
V1_q_b[14]_PORT_B_data_out = MEMORY(V1_q_b[14]_PORT_A_data_in_reg, , V1_q_b[14]_PORT_A_address_reg, V1_q_b[14]_PORT_B_address_reg, V1_q_b[14]_PORT_A_write_enable_reg, V1_q_b[14]_PORT_B_read_enable_reg, , , V1_q_b[14]_clock_0, V1_q_b[14]_clock_1, , V1_q_b[14]_clock_enable_1, , );
V1_q_b[14]_PORT_B_data_out_reg = DFFE(V1_q_b[14]_PORT_B_data_out, V1_q_b[14]_clock_1, , , V1_q_b[14]_clock_enable_1);
V1_q_b[14] = V1_q_b[14]_PORT_B_data_out_reg[0];


--V1_q_b[13] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[13]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[13]_PORT_A_data_in = S1_data[13];
V1_q_b[13]_PORT_A_data_in_reg = DFFE(V1_q_b[13]_PORT_A_data_in, V1_q_b[13]_clock_0, , , );
V1_q_b[13]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[13]_PORT_A_address_reg = DFFE(V1_q_b[13]_PORT_A_address, V1_q_b[13]_clock_0, , , );
V1_q_b[13]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[13]_PORT_B_address_reg = DFFE(V1_q_b[13]_PORT_B_address, V1_q_b[13]_clock_1, , , V1_q_b[13]_clock_enable_1);
V1_q_b[13]_PORT_A_write_enable = U1L02;
V1_q_b[13]_PORT_A_write_enable_reg = DFFE(V1_q_b[13]_PORT_A_write_enable, V1_q_b[13]_clock_0, , , );
V1_q_b[13]_PORT_B_read_enable = VCC;
V1_q_b[13]_PORT_B_read_enable_reg = DFFE(V1_q_b[13]_PORT_B_read_enable, V1_q_b[13]_clock_1, , , V1_q_b[13]_clock_enable_1);
V1_q_b[13]_clock_0 = inst11;
V1_q_b[13]_clock_1 = rdclk;
V1_q_b[13]_clock_enable_1 = U1L71;
V1_q_b[13]_PORT_B_data_out = MEMORY(V1_q_b[13]_PORT_A_data_in_reg, , V1_q_b[13]_PORT_A_address_reg, V1_q_b[13]_PORT_B_address_reg, V1_q_b[13]_PORT_A_write_enable_reg, V1_q_b[13]_PORT_B_read_enable_reg, , , V1_q_b[13]_clock_0, V1_q_b[13]_clock_1, , V1_q_b[13]_clock_enable_1, , );
V1_q_b[13]_PORT_B_data_out_reg = DFFE(V1_q_b[13]_PORT_B_data_out, V1_q_b[13]_clock_1, , , V1_q_b[13]_clock_enable_1);
V1_q_b[13] = V1_q_b[13]_PORT_B_data_out_reg[0];


--V1_q_b[12] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[12]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[12]_PORT_A_data_in = S1_data[12];
V1_q_b[12]_PORT_A_data_in_reg = DFFE(V1_q_b[12]_PORT_A_data_in, V1_q_b[12]_clock_0, , , );
V1_q_b[12]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[12]_PORT_A_address_reg = DFFE(V1_q_b[12]_PORT_A_address, V1_q_b[12]_clock_0, , , );
V1_q_b[12]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[12]_PORT_B_address_reg = DFFE(V1_q_b[12]_PORT_B_address, V1_q_b[12]_clock_1, , , V1_q_b[12]_clock_enable_1);
V1_q_b[12]_PORT_A_write_enable = U1L02;
V1_q_b[12]_PORT_A_write_enable_reg = DFFE(V1_q_b[12]_PORT_A_write_enable, V1_q_b[12]_clock_0, , , );
V1_q_b[12]_PORT_B_read_enable = VCC;
V1_q_b[12]_PORT_B_read_enable_reg = DFFE(V1_q_b[12]_PORT_B_read_enable, V1_q_b[12]_clock_1, , , V1_q_b[12]_clock_enable_1);
V1_q_b[12]_clock_0 = inst11;
V1_q_b[12]_clock_1 = rdclk;
V1_q_b[12]_clock_enable_1 = U1L71;
V1_q_b[12]_PORT_B_data_out = MEMORY(V1_q_b[12]_PORT_A_data_in_reg, , V1_q_b[12]_PORT_A_address_reg, V1_q_b[12]_PORT_B_address_reg, V1_q_b[12]_PORT_A_write_enable_reg, V1_q_b[12]_PORT_B_read_enable_reg, , , V1_q_b[12]_clock_0, V1_q_b[12]_clock_1, , V1_q_b[12]_clock_enable_1, , );
V1_q_b[12]_PORT_B_data_out_reg = DFFE(V1_q_b[12]_PORT_B_data_out, V1_q_b[12]_clock_1, , , V1_q_b[12]_clock_enable_1);
V1_q_b[12] = V1_q_b[12]_PORT_B_data_out_reg[0];


--V1_q_b[11] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[11]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[11]_PORT_A_data_in = S1_data[11];
V1_q_b[11]_PORT_A_data_in_reg = DFFE(V1_q_b[11]_PORT_A_data_in, V1_q_b[11]_clock_0, , , );
V1_q_b[11]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[11]_PORT_A_address_reg = DFFE(V1_q_b[11]_PORT_A_address, V1_q_b[11]_clock_0, , , );
V1_q_b[11]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[11]_PORT_B_address_reg = DFFE(V1_q_b[11]_PORT_B_address, V1_q_b[11]_clock_1, , , V1_q_b[11]_clock_enable_1);
V1_q_b[11]_PORT_A_write_enable = U1L02;
V1_q_b[11]_PORT_A_write_enable_reg = DFFE(V1_q_b[11]_PORT_A_write_enable, V1_q_b[11]_clock_0, , , );
V1_q_b[11]_PORT_B_read_enable = VCC;
V1_q_b[11]_PORT_B_read_enable_reg = DFFE(V1_q_b[11]_PORT_B_read_enable, V1_q_b[11]_clock_1, , , V1_q_b[11]_clock_enable_1);
V1_q_b[11]_clock_0 = inst11;
V1_q_b[11]_clock_1 = rdclk;
V1_q_b[11]_clock_enable_1 = U1L71;
V1_q_b[11]_PORT_B_data_out = MEMORY(V1_q_b[11]_PORT_A_data_in_reg, , V1_q_b[11]_PORT_A_address_reg, V1_q_b[11]_PORT_B_address_reg, V1_q_b[11]_PORT_A_write_enable_reg, V1_q_b[11]_PORT_B_read_enable_reg, , , V1_q_b[11]_clock_0, V1_q_b[11]_clock_1, , V1_q_b[11]_clock_enable_1, , );
V1_q_b[11]_PORT_B_data_out_reg = DFFE(V1_q_b[11]_PORT_B_data_out, V1_q_b[11]_clock_1, , , V1_q_b[11]_clock_enable_1);
V1_q_b[11] = V1_q_b[11]_PORT_B_data_out_reg[0];


--V1_q_b[10] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[10]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[10]_PORT_A_data_in = S1_data[10];
V1_q_b[10]_PORT_A_data_in_reg = DFFE(V1_q_b[10]_PORT_A_data_in, V1_q_b[10]_clock_0, , , );
V1_q_b[10]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[10]_PORT_A_address_reg = DFFE(V1_q_b[10]_PORT_A_address, V1_q_b[10]_clock_0, , , );
V1_q_b[10]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[10]_PORT_B_address_reg = DFFE(V1_q_b[10]_PORT_B_address, V1_q_b[10]_clock_1, , , V1_q_b[10]_clock_enable_1);
V1_q_b[10]_PORT_A_write_enable = U1L02;
V1_q_b[10]_PORT_A_write_enable_reg = DFFE(V1_q_b[10]_PORT_A_write_enable, V1_q_b[10]_clock_0, , , );
V1_q_b[10]_PORT_B_read_enable = VCC;
V1_q_b[10]_PORT_B_read_enable_reg = DFFE(V1_q_b[10]_PORT_B_read_enable, V1_q_b[10]_clock_1, , , V1_q_b[10]_clock_enable_1);
V1_q_b[10]_clock_0 = inst11;
V1_q_b[10]_clock_1 = rdclk;
V1_q_b[10]_clock_enable_1 = U1L71;
V1_q_b[10]_PORT_B_data_out = MEMORY(V1_q_b[10]_PORT_A_data_in_reg, , V1_q_b[10]_PORT_A_address_reg, V1_q_b[10]_PORT_B_address_reg, V1_q_b[10]_PORT_A_write_enable_reg, V1_q_b[10]_PORT_B_read_enable_reg, , , V1_q_b[10]_clock_0, V1_q_b[10]_clock_1, , V1_q_b[10]_clock_enable_1, , );
V1_q_b[10]_PORT_B_data_out_reg = DFFE(V1_q_b[10]_PORT_B_data_out, V1_q_b[10]_clock_1, , , V1_q_b[10]_clock_enable_1);
V1_q_b[10] = V1_q_b[10]_PORT_B_data_out_reg[0];


--V1_q_b[9] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[9]_PORT_A_data_in = S1_data[9];
V1_q_b[9]_PORT_A_data_in_reg = DFFE(V1_q_b[9]_PORT_A_data_in, V1_q_b[9]_clock_0, , , );
V1_q_b[9]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[9]_PORT_A_address_reg = DFFE(V1_q_b[9]_PORT_A_address, V1_q_b[9]_clock_0, , , );
V1_q_b[9]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[9]_PORT_B_address_reg = DFFE(V1_q_b[9]_PORT_B_address, V1_q_b[9]_clock_1, , , V1_q_b[9]_clock_enable_1);
V1_q_b[9]_PORT_A_write_enable = U1L02;
V1_q_b[9]_PORT_A_write_enable_reg = DFFE(V1_q_b[9]_PORT_A_write_enable, V1_q_b[9]_clock_0, , , );
V1_q_b[9]_PORT_B_read_enable = VCC;
V1_q_b[9]_PORT_B_read_enable_reg = DFFE(V1_q_b[9]_PORT_B_read_enable, V1_q_b[9]_clock_1, , , V1_q_b[9]_clock_enable_1);
V1_q_b[9]_clock_0 = inst11;
V1_q_b[9]_clock_1 = rdclk;
V1_q_b[9]_clock_enable_1 = U1L71;
V1_q_b[9]_PORT_B_data_out = MEMORY(V1_q_b[9]_PORT_A_data_in_reg, , V1_q_b[9]_PORT_A_address_reg, V1_q_b[9]_PORT_B_address_reg, V1_q_b[9]_PORT_A_write_enable_reg, V1_q_b[9]_PORT_B_read_enable_reg, , , V1_q_b[9]_clock_0, V1_q_b[9]_clock_1, , V1_q_b[9]_clock_enable_1, , );
V1_q_b[9]_PORT_B_data_out_reg = DFFE(V1_q_b[9]_PORT_B_data_out, V1_q_b[9]_clock_1, , , V1_q_b[9]_clock_enable_1);