429_enc_dec.map.eqn

Quartus开发环境下开发的Arinc 429总线收发器工程

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[24]_PORT_A_data_in = S1_data[24];
V1_q_b[24]_PORT_A_data_in_reg = DFFE(V1_q_b[24]_PORT_A_data_in, V1_q_b[24]_clock_0, , , );
V1_q_b[24]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[24]_PORT_A_address_reg = DFFE(V1_q_b[24]_PORT_A_address, V1_q_b[24]_clock_0, , , );
V1_q_b[24]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[24]_PORT_B_address_reg = DFFE(V1_q_b[24]_PORT_B_address, V1_q_b[24]_clock_1, , , V1_q_b[24]_clock_enable_1);
V1_q_b[24]_PORT_A_write_enable = U1L02;
V1_q_b[24]_PORT_A_write_enable_reg = DFFE(V1_q_b[24]_PORT_A_write_enable, V1_q_b[24]_clock_0, , , );
V1_q_b[24]_PORT_B_read_enable = VCC;
V1_q_b[24]_PORT_B_read_enable_reg = DFFE(V1_q_b[24]_PORT_B_read_enable, V1_q_b[24]_clock_1, , , V1_q_b[24]_clock_enable_1);
V1_q_b[24]_clock_0 = inst11;
V1_q_b[24]_clock_1 = rdclk;
V1_q_b[24]_clock_enable_1 = U1L71;
V1_q_b[24]_PORT_B_data_out = MEMORY(V1_q_b[24]_PORT_A_data_in_reg, , V1_q_b[24]_PORT_A_address_reg, V1_q_b[24]_PORT_B_address_reg, V1_q_b[24]_PORT_A_write_enable_reg, V1_q_b[24]_PORT_B_read_enable_reg, , , V1_q_b[24]_clock_0, V1_q_b[24]_clock_1, , V1_q_b[24]_clock_enable_1, , );
V1_q_b[24]_PORT_B_data_out_reg = DFFE(V1_q_b[24]_PORT_B_data_out, V1_q_b[24]_clock_1, , , V1_q_b[24]_clock_enable_1);
V1_q_b[24] = V1_q_b[24]_PORT_B_data_out_reg[0];


--V1_q_b[23] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[23]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[23]_PORT_A_data_in = S1_data[23];
V1_q_b[23]_PORT_A_data_in_reg = DFFE(V1_q_b[23]_PORT_A_data_in, V1_q_b[23]_clock_0, , , );
V1_q_b[23]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[23]_PORT_A_address_reg = DFFE(V1_q_b[23]_PORT_A_address, V1_q_b[23]_clock_0, , , );
V1_q_b[23]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[23]_PORT_B_address_reg = DFFE(V1_q_b[23]_PORT_B_address, V1_q_b[23]_clock_1, , , V1_q_b[23]_clock_enable_1);
V1_q_b[23]_PORT_A_write_enable = U1L02;
V1_q_b[23]_PORT_A_write_enable_reg = DFFE(V1_q_b[23]_PORT_A_write_enable, V1_q_b[23]_clock_0, , , );
V1_q_b[23]_PORT_B_read_enable = VCC;
V1_q_b[23]_PORT_B_read_enable_reg = DFFE(V1_q_b[23]_PORT_B_read_enable, V1_q_b[23]_clock_1, , , V1_q_b[23]_clock_enable_1);
V1_q_b[23]_clock_0 = inst11;
V1_q_b[23]_clock_1 = rdclk;
V1_q_b[23]_clock_enable_1 = U1L71;
V1_q_b[23]_PORT_B_data_out = MEMORY(V1_q_b[23]_PORT_A_data_in_reg, , V1_q_b[23]_PORT_A_address_reg, V1_q_b[23]_PORT_B_address_reg, V1_q_b[23]_PORT_A_write_enable_reg, V1_q_b[23]_PORT_B_read_enable_reg, , , V1_q_b[23]_clock_0, V1_q_b[23]_clock_1, , V1_q_b[23]_clock_enable_1, , );
V1_q_b[23]_PORT_B_data_out_reg = DFFE(V1_q_b[23]_PORT_B_data_out, V1_q_b[23]_clock_1, , , V1_q_b[23]_clock_enable_1);
V1_q_b[23] = V1_q_b[23]_PORT_B_data_out_reg[0];


--V1_q_b[22] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[22]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[22]_PORT_A_data_in = S1_data[22];
V1_q_b[22]_PORT_A_data_in_reg = DFFE(V1_q_b[22]_PORT_A_data_in, V1_q_b[22]_clock_0, , , );
V1_q_b[22]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[22]_PORT_A_address_reg = DFFE(V1_q_b[22]_PORT_A_address, V1_q_b[22]_clock_0, , , );
V1_q_b[22]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[22]_PORT_B_address_reg = DFFE(V1_q_b[22]_PORT_B_address, V1_q_b[22]_clock_1, , , V1_q_b[22]_clock_enable_1);
V1_q_b[22]_PORT_A_write_enable = U1L02;
V1_q_b[22]_PORT_A_write_enable_reg = DFFE(V1_q_b[22]_PORT_A_write_enable, V1_q_b[22]_clock_0, , , );
V1_q_b[22]_PORT_B_read_enable = VCC;
V1_q_b[22]_PORT_B_read_enable_reg = DFFE(V1_q_b[22]_PORT_B_read_enable, V1_q_b[22]_clock_1, , , V1_q_b[22]_clock_enable_1);
V1_q_b[22]_clock_0 = inst11;
V1_q_b[22]_clock_1 = rdclk;
V1_q_b[22]_clock_enable_1 = U1L71;
V1_q_b[22]_PORT_B_data_out = MEMORY(V1_q_b[22]_PORT_A_data_in_reg, , V1_q_b[22]_PORT_A_address_reg, V1_q_b[22]_PORT_B_address_reg, V1_q_b[22]_PORT_A_write_enable_reg, V1_q_b[22]_PORT_B_read_enable_reg, , , V1_q_b[22]_clock_0, V1_q_b[22]_clock_1, , V1_q_b[22]_clock_enable_1, , );
V1_q_b[22]_PORT_B_data_out_reg = DFFE(V1_q_b[22]_PORT_B_data_out, V1_q_b[22]_clock_1, , , V1_q_b[22]_clock_enable_1);
V1_q_b[22] = V1_q_b[22]_PORT_B_data_out_reg[0];


--V1_q_b[21] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[21]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[21]_PORT_A_data_in = S1_data[21];
V1_q_b[21]_PORT_A_data_in_reg = DFFE(V1_q_b[21]_PORT_A_data_in, V1_q_b[21]_clock_0, , , );
V1_q_b[21]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[21]_PORT_A_address_reg = DFFE(V1_q_b[21]_PORT_A_address, V1_q_b[21]_clock_0, , , );
V1_q_b[21]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[21]_PORT_B_address_reg = DFFE(V1_q_b[21]_PORT_B_address, V1_q_b[21]_clock_1, , , V1_q_b[21]_clock_enable_1);
V1_q_b[21]_PORT_A_write_enable = U1L02;
V1_q_b[21]_PORT_A_write_enable_reg = DFFE(V1_q_b[21]_PORT_A_write_enable, V1_q_b[21]_clock_0, , , );
V1_q_b[21]_PORT_B_read_enable = VCC;
V1_q_b[21]_PORT_B_read_enable_reg = DFFE(V1_q_b[21]_PORT_B_read_enable, V1_q_b[21]_clock_1, , , V1_q_b[21]_clock_enable_1);
V1_q_b[21]_clock_0 = inst11;
V1_q_b[21]_clock_1 = rdclk;
V1_q_b[21]_clock_enable_1 = U1L71;
V1_q_b[21]_PORT_B_data_out = MEMORY(V1_q_b[21]_PORT_A_data_in_reg, , V1_q_b[21]_PORT_A_address_reg, V1_q_b[21]_PORT_B_address_reg, V1_q_b[21]_PORT_A_write_enable_reg, V1_q_b[21]_PORT_B_read_enable_reg, , , V1_q_b[21]_clock_0, V1_q_b[21]_clock_1, , V1_q_b[21]_clock_enable_1, , );
V1_q_b[21]_PORT_B_data_out_reg = DFFE(V1_q_b[21]_PORT_B_data_out, V1_q_b[21]_clock_1, , , V1_q_b[21]_clock_enable_1);
V1_q_b[21] = V1_q_b[21]_PORT_B_data_out_reg[0];


--V1_q_b[20] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[20]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[20]_PORT_A_data_in = S1_data[20];
V1_q_b[20]_PORT_A_data_in_reg = DFFE(V1_q_b[20]_PORT_A_data_in, V1_q_b[20]_clock_0, , , );
V1_q_b[20]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[20]_PORT_A_address_reg = DFFE(V1_q_b[20]_PORT_A_address, V1_q_b[20]_clock_0, , , );
V1_q_b[20]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[20]_PORT_B_address_reg = DFFE(V1_q_b[20]_PORT_B_address, V1_q_b[20]_clock_1, , , V1_q_b[20]_clock_enable_1);
V1_q_b[20]_PORT_A_write_enable = U1L02;
V1_q_b[20]_PORT_A_write_enable_reg = DFFE(V1_q_b[20]_PORT_A_write_enable, V1_q_b[20]_clock_0, , , );
V1_q_b[20]_PORT_B_read_enable = VCC;
V1_q_b[20]_PORT_B_read_enable_reg = DFFE(V1_q_b[20]_PORT_B_read_enable, V1_q_b[20]_clock_1, , , V1_q_b[20]_clock_enable_1);
V1_q_b[20]_clock_0 = inst11;
V1_q_b[20]_clock_1 = rdclk;
V1_q_b[20]_clock_enable_1 = U1L71;
V1_q_b[20]_PORT_B_data_out = MEMORY(V1_q_b[20]_PORT_A_data_in_reg, , V1_q_b[20]_PORT_A_address_reg, V1_q_b[20]_PORT_B_address_reg, V1_q_b[20]_PORT_A_write_enable_reg, V1_q_b[20]_PORT_B_read_enable_reg, , , V1_q_b[20]_clock_0, V1_q_b[20]_clock_1, , V1_q_b[20]_clock_enable_1, , );
V1_q_b[20]_PORT_B_data_out_reg = DFFE(V1_q_b[20]_PORT_B_data_out, V1_q_b[20]_clock_1, , , V1_q_b[20]_clock_enable_1);
V1_q_b[20] = V1_q_b[20]_PORT_B_data_out_reg[0];


--V1_q_b[19] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[19]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[19]_PORT_A_data_in = S1_data[19];
V1_q_b[19]_PORT_A_data_in_reg = DFFE(V1_q_b[19]_PORT_A_data_in, V1_q_b[19]_clock_0, , , );
V1_q_b[19]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[19]_PORT_A_address_reg = DFFE(V1_q_b[19]_PORT_A_address, V1_q_b[19]_clock_0, , , );
V1_q_b[19]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[19]_PORT_B_address_reg = DFFE(V1_q_b[19]_PORT_B_address, V1_q_b[19]_clock_1, , , V1_q_b[19]_clock_enable_1);
V1_q_b[19]_PORT_A_write_enable = U1L02;
V1_q_b[19]_PORT_A_write_enable_reg = DFFE(V1_q_b[19]_PORT_A_write_enable, V1_q_b[19]_clock_0, , , );
V1_q_b[19]_PORT_B_read_enable = VCC;
V1_q_b[19]_PORT_B_read_enable_reg = DFFE(V1_q_b[19]_PORT_B_read_enable, V1_q_b[19]_clock_1, , , V1_q_b[19]_clock_enable_1);
V1_q_b[19]_clock_0 = inst11;
V1_q_b[19]_clock_1 = rdclk;
V1_q_b[19]_clock_enable_1 = U1L71;
V1_q_b[19]_PORT_B_data_out = MEMORY(V1_q_b[19]_PORT_A_data_in_reg, , V1_q_b[19]_PORT_A_address_reg, V1_q_b[19]_PORT_B_address_reg, V1_q_b[19]_PORT_A_write_enable_reg, V1_q_b[19]_PORT_B_read_enable_reg, , , V1_q_b[19]_clock_0, V1_q_b[19]_clock_1, , V1_q_b[19]_clock_enable_1, , );
V1_q_b[19]_PORT_B_data_out_reg = DFFE(V1_q_b[19]_PORT_B_data_out, V1_q_b[19]_clock_1, , , V1_q_b[19]_clock_enable_1);
V1_q_b[19] = V1_q_b[19]_PORT_B_data_out_reg[0];


--V1_q_b[18] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[18]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[18]_PORT_A_data_in = S1_data[18];
V1_q_b[18]_PORT_A_data_in_reg = DFFE(V1_q_b[18]_PORT_A_data_in, V1_q_b[18]_clock_0, , , );
V1_q_b[18]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[18]_PORT_A_address_reg = DFFE(V1_q_b[18]_PORT_A_address, V1_q_b[18]_clock_0, , , );
V1_q_b[18]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[18]_PORT_B_address_reg = DFFE(V1_q_b[18]_PORT_B_address, V1_q_b[18]_clock_1, , , V1_q_b[18]_clock_enable_1);
V1_q_b[18]_PORT_A_write_enable = U1L02;
V1_q_b[18]_PORT_A_write_enable_reg = DFFE(V1_q_b[18]_PORT_A_write_enable, V1_q_b[18]_clock_0, , , );
V1_q_b[18]_PORT_B_read_enable = VCC;
V1_q_b[18]_PORT_B_read_enable_reg = DFFE(V1_q_b[18]_PORT_B_read_enable, V1_q_b[18]_clock_1, , , V1_q_b[18]_clock_enable_1);
V1_q_b[18]_clock_0 = inst11;
V1_q_b[18]_clock_1 = rdclk;
V1_q_b[18]_clock_enable_1 = U1L71;
V1_q_b[18]_PORT_B_data_out = MEMORY(V1_q_b[18]_PORT_A_data_in_reg, , V1_q_b[18]_PORT_A_address_reg, V1_q_b[18]_PORT_B_address_reg, V1_q_b[18]_PORT_A_write_enable_reg, V1_q_b[18]_PORT_B_read_enable_reg, , , V1_q_b[18]_clock_0, V1_q_b[18]_clock_1, , V1_q_b[18]_clock_enable_1, , );
V1_q_b[18]_PORT_B_data_out_reg = DFFE(V1_q_b[18]_PORT_B_data_out, V1_q_b[18]_clock_1, , , V1_q_b[18]_clock_enable_1);
V1_q_b[18] = V1_q_b[18]_PORT_B_data_out_reg[0];


--V1_q_b[17] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[17]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[17]_PORT_A_data_in = S1_data[17];
V1_q_b[17]_PORT_A_data_in_reg = DFFE(V1_q_b[17]_PORT_A_data_in, V1_q_b[17]_clock_0, , , );
V1_q_b[17]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[17]_PORT_A_address_reg = DFFE(V1_q_b[17]_PORT_A_address, V1_q_b[17]_clock_0, , , );
V1_q_b[17]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[17]_PORT_B_address_reg = DFFE(V1_q_b[17]_PORT_B_address, V1_q_b[17]_clock_1, , , V1_q_b[17]_clock_enable_1);
V1_q_b[17]_PORT_A_write_enable = U1L02;
V1_q_b[17]_PORT_A_write_enable_reg = DFFE(V1_q_b[17]_PORT_A_write_enable, V1_q_b[17]_clock_0, , , );
V1_q_b[17]_PORT_B_read_enable = VCC;
V1_q_b[17]_PORT_B_read_enable_reg = DFFE(V1_q_b[17]_PORT_B_read_enable, V1_q_b[17]_clock_1, , , V1_q_b[17]_clock_enable_1);
V1_q_b[17]_clock_0 = inst11;
V1_q_b[17]_clock_1 = rdclk;
V1_q_b[17]_clock_enable_1 = U1L71;
V1_q_b[17]_PORT_B_data_out = MEMORY(V1_q_b[17]_PORT_A_data_in_reg, , V1_q_b[17]_PORT_A_address_reg, V1_q_b[17]_PORT_B_address_reg, V1_q_b[17]_PORT_A_write_enable_reg, V1_q_b[17]_PORT_B_read_enable_reg, , , V1_q_b[17]_clock_0, V1_q_b[17]_clock_1, , V1_q_b[17]_clock_enable_1, , );
V1_q_b[17]_PORT_B_data_out_reg = DFFE(V1_q_b[17]_PORT_B_data_out, V1_q_b[17]_clock_1, , , V1_q_b[17]_clock_enable_1);
V1_q_b[17] = V1_q_b[17]_PORT_B_data_out_reg[0];