429_enc_dec.map.eqn

Quartus开发环境下开发的Arinc 429总线收发器工程

--S1_data[2] is data_sfr:inst8|data_lath:data_lath1|data[2]
S1_data[2]_D_input = K1_data_out[2];
S1_data[2] = DFFE(S1_data[2]_D_input, P3_Q,  ,  ,  );


--S1_data[1] is data_sfr:inst8|data_lath:data_lath1|data[1]
S1_data[1]_D_input = K1_data_out[1];
S1_data[1] = DFFE(S1_data[1]_D_input, P3_Q,  ,  ,  );


--S1_data[0] is data_sfr:inst8|data_lath:data_lath1|data[0]
S1_data[0]_D_input = K1L53;
S1_data[0] = DFFE(S1_data[0]_D_input, P3_Q,  ,  ,  );


--V1_q_b[31] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[31]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[31]_PORT_A_data_in = S1_data[31];
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L02;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = inst11;
V1_q_b[31]_clock_1 = rdclk;
V1_q_b[31]_clock_enable_1 = U1L71;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31] = V1_q_b[31]_PORT_B_data_out_reg[0];


--V1_q_b[30] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[30]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[30]_PORT_A_data_in = S1_data[30];
V1_q_b[30]_PORT_A_data_in_reg = DFFE(V1_q_b[30]_PORT_A_data_in, V1_q_b[30]_clock_0, , , );
V1_q_b[30]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[30]_PORT_A_address_reg = DFFE(V1_q_b[30]_PORT_A_address, V1_q_b[30]_clock_0, , , );
V1_q_b[30]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[30]_PORT_B_address_reg = DFFE(V1_q_b[30]_PORT_B_address, V1_q_b[30]_clock_1, , , V1_q_b[30]_clock_enable_1);
V1_q_b[30]_PORT_A_write_enable = U1L02;
V1_q_b[30]_PORT_A_write_enable_reg = DFFE(V1_q_b[30]_PORT_A_write_enable, V1_q_b[30]_clock_0, , , );
V1_q_b[30]_PORT_B_read_enable = VCC;
V1_q_b[30]_PORT_B_read_enable_reg = DFFE(V1_q_b[30]_PORT_B_read_enable, V1_q_b[30]_clock_1, , , V1_q_b[30]_clock_enable_1);
V1_q_b[30]_clock_0 = inst11;
V1_q_b[30]_clock_1 = rdclk;
V1_q_b[30]_clock_enable_1 = U1L71;
V1_q_b[30]_PORT_B_data_out = MEMORY(V1_q_b[30]_PORT_A_data_in_reg, , V1_q_b[30]_PORT_A_address_reg, V1_q_b[30]_PORT_B_address_reg, V1_q_b[30]_PORT_A_write_enable_reg, V1_q_b[30]_PORT_B_read_enable_reg, , , V1_q_b[30]_clock_0, V1_q_b[30]_clock_1, , V1_q_b[30]_clock_enable_1, , );
V1_q_b[30]_PORT_B_data_out_reg = DFFE(V1_q_b[30]_PORT_B_data_out, V1_q_b[30]_clock_1, , , V1_q_b[30]_clock_enable_1);
V1_q_b[30] = V1_q_b[30]_PORT_B_data_out_reg[0];


--V1_q_b[29] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[29]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[29]_PORT_A_data_in = S1_data[29];
V1_q_b[29]_PORT_A_data_in_reg = DFFE(V1_q_b[29]_PORT_A_data_in, V1_q_b[29]_clock_0, , , );
V1_q_b[29]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[29]_PORT_A_address_reg = DFFE(V1_q_b[29]_PORT_A_address, V1_q_b[29]_clock_0, , , );
V1_q_b[29]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[29]_PORT_B_address_reg = DFFE(V1_q_b[29]_PORT_B_address, V1_q_b[29]_clock_1, , , V1_q_b[29]_clock_enable_1);
V1_q_b[29]_PORT_A_write_enable = U1L02;
V1_q_b[29]_PORT_A_write_enable_reg = DFFE(V1_q_b[29]_PORT_A_write_enable, V1_q_b[29]_clock_0, , , );
V1_q_b[29]_PORT_B_read_enable = VCC;
V1_q_b[29]_PORT_B_read_enable_reg = DFFE(V1_q_b[29]_PORT_B_read_enable, V1_q_b[29]_clock_1, , , V1_q_b[29]_clock_enable_1);
V1_q_b[29]_clock_0 = inst11;
V1_q_b[29]_clock_1 = rdclk;
V1_q_b[29]_clock_enable_1 = U1L71;
V1_q_b[29]_PORT_B_data_out = MEMORY(V1_q_b[29]_PORT_A_data_in_reg, , V1_q_b[29]_PORT_A_address_reg, V1_q_b[29]_PORT_B_address_reg, V1_q_b[29]_PORT_A_write_enable_reg, V1_q_b[29]_PORT_B_read_enable_reg, , , V1_q_b[29]_clock_0, V1_q_b[29]_clock_1, , V1_q_b[29]_clock_enable_1, , );
V1_q_b[29]_PORT_B_data_out_reg = DFFE(V1_q_b[29]_PORT_B_data_out, V1_q_b[29]_clock_1, , , V1_q_b[29]_clock_enable_1);
V1_q_b[29] = V1_q_b[29]_PORT_B_data_out_reg[0];


--V1_q_b[28] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[28]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[28]_PORT_A_data_in = S1_data[28];
V1_q_b[28]_PORT_A_data_in_reg = DFFE(V1_q_b[28]_PORT_A_data_in, V1_q_b[28]_clock_0, , , );
V1_q_b[28]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[28]_PORT_A_address_reg = DFFE(V1_q_b[28]_PORT_A_address, V1_q_b[28]_clock_0, , , );
V1_q_b[28]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[28]_PORT_B_address_reg = DFFE(V1_q_b[28]_PORT_B_address, V1_q_b[28]_clock_1, , , V1_q_b[28]_clock_enable_1);
V1_q_b[28]_PORT_A_write_enable = U1L02;
V1_q_b[28]_PORT_A_write_enable_reg = DFFE(V1_q_b[28]_PORT_A_write_enable, V1_q_b[28]_clock_0, , , );
V1_q_b[28]_PORT_B_read_enable = VCC;
V1_q_b[28]_PORT_B_read_enable_reg = DFFE(V1_q_b[28]_PORT_B_read_enable, V1_q_b[28]_clock_1, , , V1_q_b[28]_clock_enable_1);
V1_q_b[28]_clock_0 = inst11;
V1_q_b[28]_clock_1 = rdclk;
V1_q_b[28]_clock_enable_1 = U1L71;
V1_q_b[28]_PORT_B_data_out = MEMORY(V1_q_b[28]_PORT_A_data_in_reg, , V1_q_b[28]_PORT_A_address_reg, V1_q_b[28]_PORT_B_address_reg, V1_q_b[28]_PORT_A_write_enable_reg, V1_q_b[28]_PORT_B_read_enable_reg, , , V1_q_b[28]_clock_0, V1_q_b[28]_clock_1, , V1_q_b[28]_clock_enable_1, , );
V1_q_b[28]_PORT_B_data_out_reg = DFFE(V1_q_b[28]_PORT_B_data_out, V1_q_b[28]_clock_1, , , V1_q_b[28]_clock_enable_1);
V1_q_b[28] = V1_q_b[28]_PORT_B_data_out_reg[0];


--V1_q_b[27] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[27]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[27]_PORT_A_data_in = S1_data[27];
V1_q_b[27]_PORT_A_data_in_reg = DFFE(V1_q_b[27]_PORT_A_data_in, V1_q_b[27]_clock_0, , , );
V1_q_b[27]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[27]_PORT_A_address_reg = DFFE(V1_q_b[27]_PORT_A_address, V1_q_b[27]_clock_0, , , );
V1_q_b[27]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[27]_PORT_B_address_reg = DFFE(V1_q_b[27]_PORT_B_address, V1_q_b[27]_clock_1, , , V1_q_b[27]_clock_enable_1);
V1_q_b[27]_PORT_A_write_enable = U1L02;
V1_q_b[27]_PORT_A_write_enable_reg = DFFE(V1_q_b[27]_PORT_A_write_enable, V1_q_b[27]_clock_0, , , );
V1_q_b[27]_PORT_B_read_enable = VCC;
V1_q_b[27]_PORT_B_read_enable_reg = DFFE(V1_q_b[27]_PORT_B_read_enable, V1_q_b[27]_clock_1, , , V1_q_b[27]_clock_enable_1);
V1_q_b[27]_clock_0 = inst11;
V1_q_b[27]_clock_1 = rdclk;
V1_q_b[27]_clock_enable_1 = U1L71;
V1_q_b[27]_PORT_B_data_out = MEMORY(V1_q_b[27]_PORT_A_data_in_reg, , V1_q_b[27]_PORT_A_address_reg, V1_q_b[27]_PORT_B_address_reg, V1_q_b[27]_PORT_A_write_enable_reg, V1_q_b[27]_PORT_B_read_enable_reg, , , V1_q_b[27]_clock_0, V1_q_b[27]_clock_1, , V1_q_b[27]_clock_enable_1, , );
V1_q_b[27]_PORT_B_data_out_reg = DFFE(V1_q_b[27]_PORT_B_data_out, V1_q_b[27]_clock_1, , , V1_q_b[27]_clock_enable_1);
V1_q_b[27] = V1_q_b[27]_PORT_B_data_out_reg[0];


--V1_q_b[26] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[26]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[26]_PORT_A_data_in = S1_data[26];
V1_q_b[26]_PORT_A_data_in_reg = DFFE(V1_q_b[26]_PORT_A_data_in, V1_q_b[26]_clock_0, , , );
V1_q_b[26]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[26]_PORT_A_address_reg = DFFE(V1_q_b[26]_PORT_A_address, V1_q_b[26]_clock_0, , , );
V1_q_b[26]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[26]_PORT_B_address_reg = DFFE(V1_q_b[26]_PORT_B_address, V1_q_b[26]_clock_1, , , V1_q_b[26]_clock_enable_1);
V1_q_b[26]_PORT_A_write_enable = U1L02;
V1_q_b[26]_PORT_A_write_enable_reg = DFFE(V1_q_b[26]_PORT_A_write_enable, V1_q_b[26]_clock_0, , , );
V1_q_b[26]_PORT_B_read_enable = VCC;
V1_q_b[26]_PORT_B_read_enable_reg = DFFE(V1_q_b[26]_PORT_B_read_enable, V1_q_b[26]_clock_1, , , V1_q_b[26]_clock_enable_1);
V1_q_b[26]_clock_0 = inst11;
V1_q_b[26]_clock_1 = rdclk;
V1_q_b[26]_clock_enable_1 = U1L71;
V1_q_b[26]_PORT_B_data_out = MEMORY(V1_q_b[26]_PORT_A_data_in_reg, , V1_q_b[26]_PORT_A_address_reg, V1_q_b[26]_PORT_B_address_reg, V1_q_b[26]_PORT_A_write_enable_reg, V1_q_b[26]_PORT_B_read_enable_reg, , , V1_q_b[26]_clock_0, V1_q_b[26]_clock_1, , V1_q_b[26]_clock_enable_1, , );
V1_q_b[26]_PORT_B_data_out_reg = DFFE(V1_q_b[26]_PORT_B_data_out, V1_q_b[26]_clock_1, , , V1_q_b[26]_clock_enable_1);
V1_q_b[26] = V1_q_b[26]_PORT_B_data_out_reg[0];


--V1_q_b[25] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[25]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[25]_PORT_A_data_in = S1_data[25];
V1_q_b[25]_PORT_A_data_in_reg = DFFE(V1_q_b[25]_PORT_A_data_in, V1_q_b[25]_clock_0, , , );
V1_q_b[25]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[25]_PORT_A_address_reg = DFFE(V1_q_b[25]_PORT_A_address, V1_q_b[25]_clock_0, , , );
V1_q_b[25]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[25]_PORT_B_address_reg = DFFE(V1_q_b[25]_PORT_B_address, V1_q_b[25]_clock_1, , , V1_q_b[25]_clock_enable_1);
V1_q_b[25]_PORT_A_write_enable = U1L02;
V1_q_b[25]_PORT_A_write_enable_reg = DFFE(V1_q_b[25]_PORT_A_write_enable, V1_q_b[25]_clock_0, , , );
V1_q_b[25]_PORT_B_read_enable = VCC;
V1_q_b[25]_PORT_B_read_enable_reg = DFFE(V1_q_b[25]_PORT_B_read_enable, V1_q_b[25]_clock_1, , , V1_q_b[25]_clock_enable_1);
V1_q_b[25]_clock_0 = inst11;
V1_q_b[25]_clock_1 = rdclk;
V1_q_b[25]_clock_enable_1 = U1L71;
V1_q_b[25]_PORT_B_data_out = MEMORY(V1_q_b[25]_PORT_A_data_in_reg, , V1_q_b[25]_PORT_A_address_reg, V1_q_b[25]_PORT_B_address_reg, V1_q_b[25]_PORT_A_write_enable_reg, V1_q_b[25]_PORT_B_read_enable_reg, , , V1_q_b[25]_clock_0, V1_q_b[25]_clock_1, , V1_q_b[25]_clock_enable_1, , );
V1_q_b[25]_PORT_B_data_out_reg = DFFE(V1_q_b[25]_PORT_B_data_out, V1_q_b[25]_clock_1, , , V1_q_b[25]_clock_enable_1);
V1_q_b[25] = V1_q_b[25]_PORT_B_data_out_reg[0];


--V1_q_b[24] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[24]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1