clk_div.v

Quartus开发环境下开发的Arinc 429总线收发器工程

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
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// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
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// Generated by Quartus II Version 4.1 (Build Build 181 06/29/2004)
// Created on Thu Mar 06 08:45:22 2008

//  Module Declaration
module clk_div
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	rst_n, clk, clk_rate, clk_in, bclk
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input clk;
	input rst_n;
	input clk_rate;
	output clk_in;
	output bclk;

	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
reg [6:0]  cnt;
reg     clk_in;
// wire     rst_n;
// wire     bclk;

always @(posedge clk or negedge rst_n) begin
   if (!rst_n ) begin   
      cnt <= 7'd0 ;
      clk_in <= 'd0 ;
   end
   else if(cnt=='d39 & clk_rate) begin   
      cnt <= 7'd0 ;
      clk_in <= ~clk_in ;
   end
   else if(cnt=='d4 & !clk_rate) begin   
      cnt <= 7'd0 ;
       clk_in <= ~clk_in ;
   end
   else cnt <= cnt+7'd1 ;
 
  end
 bclk_gen  b1(rst_n, clk_in, bclk );

endmodule

module     bclk_gen(rst_n, clk_in, bclk );
input      rst_n;
input      clk_in;
output     bclk;

reg        bclk;
reg[1:0]   bcnt;

always @(posedge clk_in or negedge rst_n) begin
 if (!rst_n ) begin   
     bcnt <= 2'd0;
   end
else if(bcnt=='d3 ) begin   
      bcnt <= 2'd0 ;
      bclk <= ~bclk ;
   end
else  bcnt <= bcnt+2'd1 ;
end

endmodule