429_enc_dec.qsf

Quartus开发环境下开发的Arinc 429总线收发器工程

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		429_enc_dec_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:55:53  MARCH 06, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 4.1
set_global_assignment -name VERILOG_FILE null1sfr.v
set_global_assignment -name BDF_FILE 429_enc_dec.bdf
set_global_assignment -name VERILOG_FILE rx_input.v
set_global_assignment -name VECTOR_WAVEFORM_FILE ../1553_enc_dec/429_enc_dec.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE 429_enc_dec.vwf
set_global_assignment -name VERILOG_FILE clk_div.v
set_global_assignment -name VERILOG_FILE zerossfr.v
set_global_assignment -name VERILOG_FILE word_gap_timer.v
set_global_assignment -name VERILOG_FILE seq_ctr.v
set_global_assignment -name VERILOG_FILE R_SY_D_FF.v
set_global_assignment -name VERILOG_FILE bit_cnt.v
set_global_assignment -name VERILOG_FILE data_sfr.v
set_global_assignment -name VERILOG_FILE parity_check.v

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name SPEED_DISK_USAGE_TRADEOFF SMART
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
set_global_assignment -name IGNORE_LCELL_BUFFERS ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name TOP_LEVEL_ENTITY 429_enc_dec

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP2C5Q208C7
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name SEED 2

# Timing Analysis Assignments
# ===========================
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS ON

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT on
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_FILE atom_netlists/429_enc_dec.vqm

# -----------------
# start CLOCK(clk1)

	# Timing Assignments
	# ==================
	set_global_assignment -name FMAX_REQUIREMENT "8.0 MHz" -section_id clk1
	set_global_assignment -name DUTY_CYCLE 50 -section_id clk1
	set_global_assignment -name INVERT_BASE_CLOCK OFF -section_id clk1
	set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id clk1
	set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id clk1

# end CLOCK(clk1)
# ---------------

# -------------------------
# start ENTITY(429_enc_dec)

	# Timing Assignments
	# ==================
	set_instance_assignment -name CLOCK_SETTINGS clk1 -to clk
	set_instance_assignment -name CLOCK_SETTINGS clk2 -to bclk
	set_instance_assignment -name CLOCK_SETTINGS clk3 -to bit_clk
	set_instance_assignment -name CLOCK_SETTINGS clk3 -to clk_in

# end ENTITY(429_enc_dec)
# -----------------------