429_enc_dec.vqm

Quartus开发环境下开发的Arinc 429总线收发器工程

	.aclr(\__ALT_INV__rst_n~combout ),
	.sload(vcc),
	.regout(\zerossfr:inst4|zeros_sfr[7] ));

cycloneii_lcell_ff \zerossfr:inst4|zeros_sfr[8]~I (
	.clk(\clk_div:inst1|clk_in~clkctrl ),
	.datain(\zerossfr:inst4|zeros_sfr[8]~feeder ),
	.aclr(\__ALT_INV__rst_n~combout ),
	.regout(\zerossfr:inst4|zeros_sfr[8] ));

cycloneii_lcell_ff \zerossfr:inst4|zeros_sfr[9]~I (
	.clk(\clk_div:inst1|clk_in~clkctrl ),
	.datain(\zerossfr:inst4|zeros_sfr[9]~feeder ),
	.aclr(\__ALT_INV__rst_n~combout ),
	.regout(\zerossfr:inst4|zeros_sfr[9] ));

cycloneii_clkctrl \clk_div:inst1|bclk_gen:b1|bclk~clkctrl_I (
	.inclk({inclk_unconnected_wire_0,inclk_unconnected_wire_1,inclk_unconnected_wire_2,\clk_div:inst1|bclk_gen:b1|bclk }),
	.outclk(\clk_div:inst1|bclk_gen:b1|bclk~clkctrl ));
defparam \clk_div:inst1|bclk_gen:b1|bclk~clkctrl_I .clock_type = "Global Clock";
defparam \clk_div:inst1|bclk_gen:b1|bclk~clkctrl_I .ena_register_mode = "falling edge";

cycloneii_clkctrl \clk_div:inst1|clk_in~clkctrl_I (
	.inclk({inclk_unconnected_wire_3,inclk_unconnected_wire_4,inclk_unconnected_wire_5,\clk_div:inst1|clk_in }),
	.outclk(\clk_div:inst1|clk_in~clkctrl ));
defparam \clk_div:inst1|clk_in~clkctrl_I .clock_type = "Global Clock";
defparam \clk_div:inst1|clk_in~clkctrl_I .ena_register_mode = "falling edge";

cycloneii_lcell_comb \data_sfr:inst8|data_out[21]~feeder_I (
	.dataa(\data_sfr:inst8|data_out[20] ),
	.combout(\data_sfr:inst8|data_out[21]~feeder ));
defparam \data_sfr:inst8|data_out[21]~feeder_I .sum_lutc_input = "datac";
defparam \data_sfr:inst8|data_out[21]~feeder_I .lut_mask = "AAAA";

cycloneii_lcell_comb \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|delayed_wrptr_g[3]~feeder_I (
	.datad(\lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|wrptr_g[3] ),
	.combout(\lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|delayed_wrptr_g[3]~feeder ));
defparam \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|delayed_wrptr_g[3]~feeder_I .sum_lutc_input = "datac";
defparam \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|delayed_wrptr_g[3]~feeder_I .lut_mask = "FF00";

cycloneii_lcell_comb \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|alt_synch_pipe_h62:rs_dgwp|dffpipe_h62:dffpipe2|dffe3a[4]~feeder_I (
	.datad(\lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|delayed_wrptr_g[4] ),
	.combout(\lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|alt_synch_pipe_h62:rs_dgwp|dffpipe_h62:dffpipe2|dffe3a[4]~feeder ));
defparam \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|alt_synch_pipe_h62:rs_dgwp|dffpipe_h62:dffpipe2|dffe3a[4]~feeder_I .sum_lutc_input = "datac";
defparam \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|alt_synch_pipe_h62:rs_dgwp|dffpipe_h62:dffpipe2|dffe3a[4]~feeder_I .lut_mask = "FF00";

cycloneii_lcell_comb \null1sfr:inst3|null1_sfr[1]~feeder_I (
	.datad(\null1sfr:inst3|null1_sfr[2] ),
	.combout(\null1sfr:inst3|null1_sfr[1]~feeder ));
defparam \null1sfr:inst3|null1_sfr[1]~feeder_I .sum_lutc_input = "datac";
defparam \null1sfr:inst3|null1_sfr[1]~feeder_I .lut_mask = "FF00";

cycloneii_lcell_comb \zerossfr:inst4|zeros_sfr[5]~feeder_I (
	.datad(\zerossfr:inst4|zeros_sfr[6] ),
	.combout(\zerossfr:inst4|zeros_sfr[5]~feeder ));
defparam \zerossfr:inst4|zeros_sfr[5]~feeder_I .sum_lutc_input = "datac";
defparam \zerossfr:inst4|zeros_sfr[5]~feeder_I .lut_mask = "FF00";

cycloneii_lcell_comb \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[3]~feeder_I (
	.datab(\bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita3 ),
	.combout(\bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[3]~feeder ));
defparam \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[3]~feeder_I .sum_lutc_input = "datac";
defparam \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[3]~feeder_I .lut_mask = "CCCC";

cycloneii_lcell_comb \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[0]~feeder_I (
	.dataa(\bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita0 ),
	.combout(\bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[0]~feeder ));
defparam \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[0]~feeder_I .sum_lutc_input = "datac";
defparam \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[0]~feeder_I .lut_mask = "AAAA";

cycloneii_lcell_comb \zerossfr:inst4|zeros_sfr[8]~feeder_I (
	.datad(\zerossfr:inst4|zeros_sfr[9] ),
	.combout(\zerossfr:inst4|zeros_sfr[8]~feeder ));
defparam \zerossfr:inst4|zeros_sfr[8]~feeder_I .sum_lutc_input = "datac";
defparam \zerossfr:inst4|zeros_sfr[8]~feeder_I .lut_mask = "FF00";

cycloneii_lcell_comb \zerossfr:inst4|zeros_sfr[9]~feeder_I (
	.datad(\rn1b~combout ),
	.combout(\zerossfr:inst4|zeros_sfr[9]~feeder ));
defparam \zerossfr:inst4|zeros_sfr[9]~feeder_I .sum_lutc_input = "datac";
defparam \zerossfr:inst4|zeros_sfr[9]~feeder_I .lut_mask = "FF00";

cycloneii_lcell_comb \zerossfr:inst4|R_SY_D_FF:d1|Q~feeder_I (
	.combout(\zerossfr:inst4|R_SY_D_FF:d1|Q~feeder ));
defparam \zerossfr:inst4|R_SY_D_FF:d1|Q~feeder_I .sum_lutc_input = "datac";
defparam \zerossfr:inst4|R_SY_D_FF:d1|Q~feeder_I .lut_mask = "FFFF";

cycloneii_io \clk~I (
	.combout(\clk~combout ),
	.padio(clk));
defparam \clk~I .operation_mode = "input";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .output_sync_reset = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .oe_power_up = "low";

cycloneii_clkctrl \clk~clkctrl_I (
	.inclk({inclk_unconnected_wire_6,inclk_unconnected_wire_7,inclk_unconnected_wire_8,\clk~combout }),
	.outclk(\clk~clkctrl ));
defparam \clk~clkctrl_I .clock_type = "Global Clock";
defparam \clk~clkctrl_I .ena_register_mode = "falling edge";

cycloneii_lcell_comb \clk_div:inst1|add~1_I (
	.datab(\clk_div:inst1|cnt[0] ),
	.datad(vcc),
	.combout(\clk_div:inst1|add~1 ),
	.cout(\clk_div:inst1|add~1COUT ));
defparam \clk_div:inst1|add~1_I .sum_lutc_input = "datac";
defparam \clk_div:inst1|add~1_I .lut_mask = "33CC";

cycloneii_lcell_comb \clk_div:inst1|cnt~14_I (
	.dataa(\clk_div:inst1|always0~82 ),
	.datac(\clk_div:inst1|add~1 ),
	.datad(\clk_div:inst1|always0~80 ),
	.combout(\clk_div:inst1|cnt~14 ));
defparam \clk_div:inst1|cnt~14_I .sum_lutc_input = "datac";
defparam \clk_div:inst1|cnt~14_I .lut_mask = "A0F0";

cycloneii_io \rst_n~I (
	.combout(\rst_n~combout ),
	.padio(rst_n));
defparam \rst_n~I .operation_mode = "input";
defparam \rst_n~I .input_register_mode = "none";
defparam \rst_n~I .output_register_mode = "none";
defparam \rst_n~I .oe_register_mode = "none";
defparam \rst_n~I .input_async_reset = "none";
defparam \rst_n~I .output_async_reset = "none";
defparam \rst_n~I .oe_async_reset = "none";
defparam \rst_n~I .input_sync_reset = "none";
defparam \rst_n~I .output_sync_reset = "none";
defparam \rst_n~I .oe_sync_reset = "none";
defparam \rst_n~I .input_power_up = "low";
defparam \rst_n~I .output_power_up = "low";
defparam \rst_n~I .oe_power_up = "low";

cycloneii_lcell_ff \clk_div:inst1|cnt[0]~I (
	.clk(\clk~clkctrl ),
	.datain(\clk_div:inst1|cnt~14 ),
	.aclr(\__ALT_INV__rst_n~combout ),
	.regout(\clk_div:inst1|cnt[0] ));

cycloneii_lcell_comb \clk_div:inst1|add~3_I (
	.datab(\clk_div:inst1|cnt[2] ),
	.datad(vcc),
	.cin(\clk_div:inst1|add~2COUT ),
	.combout(\clk_div:inst1|add~3 ),
	.cout(\clk_div:inst1|add~3COUT ));
defparam \clk_div:inst1|add~3_I .sum_lutc_input = "cin";
defparam \clk_div:inst1|add~3_I .lut_mask = "3CC0";

cycloneii_lcell_comb \clk_div:inst1|cnt~15_I (
	.dataa(\clk_div:inst1|always0~82 ),
	.datab(\clk_div:inst1|add~3 ),
	.datad(\clk_div:inst1|always0~80 ),
	.combout(\clk_div:inst1|cnt~15 ));
defparam \clk_div:inst1|cnt~15_I .sum_lutc_input = "datac";
defparam \clk_div:inst1|cnt~15_I .lut_mask = "88CC";

cycloneii_lcell_ff \clk_div:inst1|cnt[2]~I (
	.clk(\clk~clkctrl ),
	.datain(\clk_div:inst1|cnt~15 ),
	.aclr(\__ALT_INV__rst_n~combout ),
	.regout(\clk_div:inst1|cnt[2] ));

cycloneii_lcell_comb \clk_div:inst1|add~5_I (
	.datab(\clk_div:inst1|cnt[4] ),
	.datad(vcc),
	.cin(\clk_div:inst1|add~4COUT ),
	.combout(\clk_div:inst1|add~5 ),
	.cout(\clk_div:inst1|add~5COUT ));
defparam \clk_div:inst1|add~5_I .sum_lutc_input = "cin";
defparam \clk_div:inst1|add~5_I .lut_mask = "3CC0";

cycloneii_lcell_ff \clk_div:inst1|cnt[4]~I (
	.clk(\clk~clkctrl ),
	.datain(\clk_div:inst1|add~5 ),
	.aclr(\__ALT_INV__rst_n~combout ),
	.regout(\clk_div:inst1|cnt[4] ));

cycloneii_io \cr0~I (
	.combout(\cr0~combout ),
	.padio(cr0));
defparam \cr0~I .operation_mode = "input";
defparam \cr0~I .input_register_mode = "none";
defparam \cr0~I .output_register_mode = "none";
defparam \cr0~I .oe_register_mode = "none";
defparam \cr0~I .input_async_reset = "none";
defparam \cr0~I .output_async_reset = "none";
defparam \cr0~I .oe_async_reset = "none";
defparam \cr0~I .input_sync_reset = "none";
defparam \cr0~I .output_sync_reset = "none";
defparam \cr0~I .oe_sync_reset = "none";
defparam \cr0~I .input_power_up = "low";
defparam \cr0~I .output_power_up = "low";
defparam \cr0~I .oe_power_up = "low";

cycloneii_lcell_comb \clk_div:inst1|always0~81_I (
	.dataa(\clk_div:inst1|cnt[1] ),
	.datab(\clk_div:inst1|cnt[5] ),
	.datac(\clk_div:inst1|cnt[0] ),
	.datad(\cr0~combout ),
	.combout(\clk_div:inst1|always0~81 ));
defparam \clk_div:inst1|always0~81_I .sum_lutc_input = "datac";
defparam \clk_div:inst1|always0~81_I .lut_mask = "8000";

cycloneii_lcell_comb \clk_div:inst1|cnt~17_I (
	.dataa(\clk_div:inst1|add~6 ),
	.datac(\clk_div:inst1|always0~81 ),
	.datad(\clk_div:inst1|always0~80 ),
	.combout(\clk_div:inst1|cnt~17 ));
defparam \clk_div:inst1|cnt~17_I .sum_lutc_input = "datac";
defparam \clk_div:inst1|cnt~17_I .lut_mask = "0AAA";

cycloneii_lcell_ff \clk_div:inst1|cnt[5]~I (
	.clk(\clk~clkctrl ),
	.datain(\clk_div:inst1|cnt~17 ),
	.aclr(\__ALT_INV__rst_n~combout ),
	.regout(\clk_div:inst1|cnt[5] ));

cycloneii_lcell_comb \clk_div:inst1|add~7_I (
	.datad(\clk_div:inst1|cnt[6] ),
	.cin(\clk_div:inst1|add~6COUT ),
	.combout(\clk_div:inst1|add~7 ));
defparam \clk_div:inst1|add~7_I .sum_lutc_input = "cin";
defparam \clk_div:inst1|add~7_I .lut_mask = "0FF0";

cycloneii_lcell_ff \clk_div:inst1|cnt[6]~I (
	.clk(\clk~clkctrl ),
	.datain(\clk_div:inst1|add~7 ),
	.aclr(\__ALT_INV__rst_n~combout ),
	.regout(\clk_div:inst1|cnt[6] ));

cycloneii_lcell_comb \clk_div:inst1|always0~80_I (
	.dataa(\clk_div:inst1|cnt[3] ),
	.datab(\clk_div:inst1|cnt[2] ),