429_enc_dec.vqm

Quartus开发环境下开发的Arinc 429总线收发器工程

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 4.1 Build 181 06/29/2004 SJ Full Version"

// DATE "03/17/2008 10:43:51"

module 	\429_enc_dec  (
	rst_n,
	cr0,
	clk,
	rdclk,
	rn1a,
	rn1b,
	clk_in,
	word_gap,
	eos,
	bit_clk,
	par_chec,
	wrclk,
	data,
	q,
	wrusedw);
input 	rst_n;
input 	cr0;
input 	clk;
input 	rdclk;
input 	rn1a;
input 	rn1b;
output 	clk_in;
output 	word_gap;
output 	eos;
output 	bit_clk;
output 	par_chec;
output 	wrclk;
output 	[31:0] data;
output 	[31:0] q;
output 	[4:0] wrusedw;
wire \clk_div:inst1|cnt[3] ;
wire \clk_div:inst1|cnt[1] ;
wire \zerossfr:inst4|R_SY_D_FF:d1|Q ;
wire \seq_ctr:inst6|always0~0 ;
wire \data_sfr:inst8|data_out[21] ;
wire \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|valid_wrreq~44 ;
wire \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|alt_synch_pipe_h62:rs_dgwp|dffpipe_h62:dffpipe2|dffe3a[4] ;
wire \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|alt_synch_pipe_h62:rs_dgwp|dffpipe_h62:dffpipe2|dffe3a[3] ;
wire \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|valid_rdreq~53 ;
wire \clk_div:inst1|add~4 ;
wire \clk_div:inst1|cnt~16 ;
wire \clk_div:inst1|add~6 ;
wire \clk_div:inst1|add~2 ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[3] ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[0] ;
wire \onessfr:inst2|ones_sfr[0] ;
wire \onessfr:inst2|ones1_val ;
wire \zerossfr:inst4|zeros_sfr[2] ;
wire \zerossfr:inst4|zeros_sfr[6] ;
wire \zerossfr:inst4|zeros_sfr[5] ;
wire \zerossfr:inst4|zeros_sfr[4] ;
wire \zerossfr:inst4|zeros1_nval~46 ;
wire \zerossfr:inst4|zeros_sfr[1] ;
wire \zerossfr:inst4|zeros_sfr[0] ;
wire \zerossfr:inst4|zeros1_val ;
wire \zerossfr:inst4|zeros1_nval ;
wire \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|delayed_wrptr_g[3] ;
wire \null1sfr:inst3|null1_sfr[1] ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita3 ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita0 ;
wire \zerossfr:inst4|zeros_sfr[3] ;
wire \zerossfr:inst4|zeros_sfr[7] ;
wire \zerossfr:inst4|zeros_sfr[8] ;
wire \zerossfr:inst4|zeros_sfr[9] ;
wire \clk_div:inst1|bclk_gen:b1|bclk~clkctrl ;
wire \clk_div:inst1|clk_in~clkctrl ;
wire \data_sfr:inst8|data_out[21]~feeder ;
wire \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|delayed_wrptr_g[3]~feeder ;
wire \lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|alt_synch_pipe_h62:rs_dgwp|dffpipe_h62:dffpipe2|dffe3a[4]~feeder ;
wire \null1sfr:inst3|null1_sfr[1]~feeder ;
wire \zerossfr:inst4|zeros_sfr[5]~feeder ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[3]~feeder ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[0]~feeder ;
wire \zerossfr:inst4|zeros_sfr[8]~feeder ;
wire \zerossfr:inst4|zeros_sfr[9]~feeder ;
wire \zerossfr:inst4|R_SY_D_FF:d1|Q~feeder ;
wire \clk~combout ;
wire \clk~clkctrl ;
wire \clk_div:inst1|add~1 ;
wire \clk_div:inst1|cnt~14 ;
wire \rst_n~combout ;
wire \clk_div:inst1|cnt[0] ;
wire \clk_div:inst1|add~1COUT ;
wire \clk_div:inst1|add~2COUT ;
wire \clk_div:inst1|add~3 ;
wire \clk_div:inst1|cnt~15 ;
wire \clk_div:inst1|cnt[2] ;
wire \clk_div:inst1|add~3COUT ;
wire \clk_div:inst1|add~4COUT ;
wire \clk_div:inst1|add~5 ;
wire \clk_div:inst1|cnt[4] ;
wire \cr0~combout ;
wire \clk_div:inst1|always0~81 ;
wire \clk_div:inst1|cnt~17 ;
wire \clk_div:inst1|cnt[5] ;
wire \clk_div:inst1|add~5COUT ;
wire \clk_div:inst1|add~6COUT ;
wire \clk_div:inst1|add~7 ;
wire \clk_div:inst1|cnt[6] ;
wire \clk_div:inst1|always0~80 ;
wire \clk_div:inst1|always0~82 ;
wire \clk_div:inst1|clk_in~24 ;
wire \clk_div:inst1|clk_in ;
wire \clk_div:inst1|bclk_gen:b1|bclk~25 ;
wire \clk_div:inst1|bclk_gen:b1|bcnt[0]~2 ;
wire \clk_div:inst1|bclk_gen:b1|bcnt[0] ;
wire \clk_div:inst1|bclk_gen:b1|bcnt[1]~3 ;
wire \clk_div:inst1|bclk_gen:b1|bcnt[1] ;
wire \clk_div:inst1|bclk_gen:b1|bclk~24 ;
wire \clk_div:inst1|bclk_gen:b1|bclk ;
wire \rn1b~combout ;
wire \rn1a~combout ;
wire \rx_input:inst|null~0 ;
wire \null1sfr:inst3|null1_sfr[9] ;
wire \null1sfr:inst3|null1_sfr[8]~feeder ;
wire \null1sfr:inst3|null1_sfr[8] ;
wire \null1sfr:inst3|null1_sfr[7] ;
wire \null1sfr:inst3|null1_sfr[6]~feeder ;
wire \null1sfr:inst3|null1_sfr[6] ;
wire \null1sfr:inst3|null1_sfr[5] ;
wire \null1sfr:inst3|null1_sfr[4] ;
wire \null1sfr:inst3|null1_sfr[3]~feeder ;
wire \null1sfr:inst3|null1_sfr[3] ;
wire \null1sfr:inst3|null1_sfr[2]~feeder ;
wire \null1sfr:inst3|null1_sfr[2] ;
wire \null1sfr:inst3|null1_val~15 ;
wire \null1sfr:inst3|null1_sfr[1]~2 ;
wire \null1sfr:inst3|null1_val ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita0~COUT ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita1 ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[1]~feeder ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[1] ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita1~COUT ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita2 ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[2] ;
wire \word_gap_timer:inst5|always0~1 ;
wire \seq_ctr:inst6|bc_crt ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita2~COUT ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita3~COUT ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|counter_comb_bita4 ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4]~feeder ;
wire \bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4] ;
wire \bit_cnt:inst7|comb~37 ;
wire \bit_cnt:inst7|comb~0 ;
wire \bit_cnt:inst7|R_SY_D_FF1:d1|Q ;
wire \bit_cnt:inst7|R_SY_D_FF1:d2|Q ;
wire \null1sfr:inst3|R_SY_D_FF1:d3|Q ;
wire \word_gap_timer:inst5|always0~0 ;
wire \word_gap_timer:inst5|always0~0clkctrl ;
wire \word_gap_timer:inst5|word_gap~feeder ;
wire \word_gap_timer:inst5|wg_cnt~3 ;
wire \word_gap_timer:inst5|wg_cnt[0] ;
wire \word_gap_timer:inst5|wg_cnt~45 ;
wire \word_gap_timer:inst5|wg_cnt[1] ;
wire \word_gap_timer:inst5|reduce_nor~0 ;
wire \word_gap_timer:inst5|word_gap ;
wire \bit_cnt:inst7|bit_clk ;
wire \bit_cnt:inst7|bit_clk~clkctrl ;
wire \data_sfr:inst8|par_chec~feeder ;
wire \onessfr:inst2|R_SY_D_FF:d2|Q~feeder ;
wire \onessfr:inst2|ones_sfr[9]~feeder ;
wire \onessfr:inst2|ones_sfr[9] ;
wire \onessfr:inst2|ones_sfr[8]~feeder ;
wire \onessfr:inst2|ones_sfr[8] ;
wire \onessfr:inst2|ones_sfr[7]~feeder ;
wire \onessfr:inst2|ones_sfr[7] ;
wire \onessfr:inst2|ones_sfr[6] ;
wire \onessfr:inst2|ones_sfr[5]~feeder ;
wire \onessfr:inst2|ones_sfr[5] ;
wire \onessfr:inst2|ones_sfr[4] ;
wire \onessfr:inst2|ones_sfr[3] ;
wire \onessfr:inst2|ones_sfr[2] ;
wire \onessfr:inst2|ones_sfr[1] ;
wire \onessfr:inst2|ones1_nval~46 ;
wire \onessfr:inst2|ones1_nval ;
wire \onessfr:inst2|R_SY_D_FF:d2|Q ;
wire \data_sfr:inst8|par_chec ;
wire inst11;
wire \bit_cnt:inst7|R_SY_D_FF1:d2|Q~clkctrl ;
wire \data_sfr:inst8|data_out[31]~feeder ;
wire \data_sfr:inst8|data_out[31] ;
wire \data_sfr:inst8|data_lath:data_lath1|data[31]~feeder ;
wire \data_sfr:inst8|data_lath:data_lath1|data[31] ;
wire \data_sfr:inst8|data_out[30]~feeder ;
wire \data_sfr:inst8|data_out[30] ;
wire \data_sfr:inst8|data_lath:data_lath1|data[30]~feeder ;
wire \data_sfr:inst8|data_lath:data_lath1|data[30] ;
wire \data_sfr:inst8|data_out[29]~feeder ;
wire \data_sfr:inst8|data_out[29] ;
wire \data_sfr:inst8|data_lath:data_lath1|data[29]~feeder ;
wire \data_sfr:inst8|data_lath:data_lath1|data[29] ;
wire \data_sfr:inst8|data_out[28]~feeder ;
wire \data_sfr:inst8|data_out[28] ;
wire \data_sfr:inst8|data_lath:data_lath1|data[28]~feeder ;
wire \data_sfr:inst8|data_lath:data_lath1|data[28] ;
wire \data_sfr:inst8|data_out[27]~feeder ;
wire \data_sfr:inst8|data_out[27] ;
wire \data_sfr:inst8|data_lath:data_lath1|data[27]~feeder ;
wire \data_sfr:inst8|data_lath:data_lath1|data[27] ;
wire \data_sfr:inst8|data_out[25]~feeder ;
wire \data_sfr:inst8|data_out[25] ;
wire \data_sfr:inst8|data_out[26]~feeder ;
wire \data_sfr:inst8|data_out[26] ;
wire \data_sfr:inst8|data_lath:data_lath1|data[26]~feeder ;
wire \data_sfr:inst8|data_lath:data_lath1|data[26] ;
wire \data_sfr:inst8|data_lath:data_lath1|data[25]~feeder ;
wire \data_sfr:inst8|data_lath:data_lath1|data[25] ;
wire \data_sfr:inst8|data_out[24]~feeder ;
wire \data_sfr:inst8|data_out[24] ;
wire \data_sfr:inst8|data_lath:data_lath1|data[24]~feeder ;
wire \data_sfr:inst8|data_lath:data_lath1|data[24] ;
wire \data_sfr:inst8|data_out[22]~feeder ;
wire \data_sfr:inst8|data_out[22] ;
wire \data_sfr:inst8|data_out[23]~feeder ;
wire \data_sfr:inst8|data_out[23] ;
wire \data_sfr:inst8|data_lath:data_lath1|data[23]~feeder ;