429_enc_dec.map.rpt

Quartus开发环境下开发的Arinc 429总线收发器工程

; d:/altera/libraries/megafunctions/dcfifo.tdf             ; yes             ;
; d:/altera/libraries/megafunctions/lpm_counter.inc        ; yes             ;
; E:/王云山资料/fpga/429_enc_dec/db/dcfifo_vos.tdf         ; yes             ;
; E:/王云山资料/fpga/429_enc_dec/db/a_gray2bin_8cb.tdf     ; yes             ;
; E:/王云山资料/fpga/429_enc_dec/db/a_graycounter_aq5.tdf  ; yes             ;
; E:/王云山资料/fpga/429_enc_dec/db/a_graycounter_5j6.tdf  ; yes             ;
; E:/王云山资料/fpga/429_enc_dec/db/altsyncram_2hp.tdf     ; yes             ;
; E:/王云山资料/fpga/429_enc_dec/db/alt_synch_pipe_h62.tdf ; yes             ;
; E:/王云山资料/fpga/429_enc_dec/db/dffpipe_h62.tdf        ; yes             ;
; E:/王云山资料/fpga/429_enc_dec/db/dffpipe_er2.tdf        ; yes             ;
; E:/王云山资料/fpga/429_enc_dec/db/add_sub_u5c.tdf        ; yes             ;
; d:/altera/libraries/megafunctions/lpm_counter.tdf        ; yes             ;
; d:/altera/libraries/megafunctions/lpm_constant.inc       ; yes             ;
; E:/王云山资料/fpga/429_enc_dec/db/cntr_vo7.tdf           ; yes             ;
+----------------------------------------------------------+-----------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+--------------------------------------------+--------+
; Resource                                   ; Usage  ;
+--------------------------------------------+--------+
; Total combinational functions              ; 79     ;
; Logic element usage by number of inputs    ;        ;
;     -- 4 input functions                   ; 15     ;
;     -- 3 input functions                   ; 26     ;
;     -- <=2 input functions                 ; 38     ;
;         -- Combinational cells for routing ; 0      ;
; Logic elements by mode                     ;        ;
;     -- normal mode                         ; 55     ;
;     -- arithmetic mode                     ; 24     ;
; Total registers                            ; 165    ;
; I/O pins                                   ; 81     ;
; Total memory bits                          ; 1024   ;
; Maximum fan-out node                       ; inst11 ;
; Maximum fan-out                            ; 61     ;
; Total fan-out                              ; 1218   ;
; Average fan-out                            ; 3.41   ;
+--------------------------------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                         ;
+------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name                                                                                                 ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF  ;
+------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024 ; None ;
+------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Mon Mar 17 10:42:52 2008
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off 429_enc_dec -c 429_enc_dec
Info: Found 1 design units, including 1 entities, in source file null1sfr.v
    Info: Found entity 1: null1sfr
Info: Found 1 design units, including 1 entities, in source file 429_enc_dec.bdf
    Info: Found entity 1: 429_enc_dec
Info: Found 1 design units, including 1 entities, in source file rx_input.v
    Info: Found entity 1: rx_input
Info: Found 2 design units, including 2 entities, in source file clk_div.v
    Info: Found entity 1: clk_div
    Info: Found entity 2: bclk_gen
Info: Found 1 design units, including 1 entities, in source file zerossfr.v
    Info: Found entity 1: zerossfr
Info: Found 1 design units, including 1 entities, in source file word_gap_timer.v
    Info: Found entity 1: word_gap_timer
Info: Found 1 design units, including 1 entities, in source file seq_ctr.v
    Info: Found entity 1: seq_ctr
Info: Found 1 design units, including 1 entities, in source file R_SY_D_FF.v
    Info: Found entity 1: R_SY_D_FF
Info: Found 2 design units, including 2 entities, in source file bit_cnt.v
    Info: Found entity 1: bit_cnt
    Info: Found entity 2: R_SY_D_FF1
Warning: Verilog HDL or VHDL warning at data_sfr.v(74): Unconverted VERI-1097: port eos is already declared
Info: Found 2 design units, including 2 entities, in source file data_sfr.v
    Info: Found entity 1: data_sfr
    Info: Found entity 2: data_lath
Info: Found 1 design units, including 1 entities, in source file parity_check.v
    Info: Found entity 1: parity_check
Info: Using design file onessfr.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: onessfr
Info: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_fifo0
Info: Found 1 design units, including 1 entities, in source file d:/altera/libraries/megafunctions/dcfifo.tdf
    Info: Found entity 1: dcfifo
Info: Found 1 design units, including 1 entities, in source file db/dcfifo_vos.tdf
    Info: Found entity 1: dcfifo_vos
Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_8cb.tdf
    Info: Found entity 1: a_gray2bin_8cb
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_aq5.tdf
    Info: Found entity 1: a_graycounter_aq5
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_5j6.tdf
    Info: Found entity 1: a_graycounter_5j6
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_2hp.tdf
    Info: Found entity 1: altsyncram_2hp
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_h62.tdf
    Info: Found entity 1: alt_synch_pipe_h62
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_h62.tdf
    Info: Found entity 1: dffpipe_h62
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_er2.tdf
    Info: Found entity 1: dffpipe_er2
Info: Found 1 design units, including 1 entities, in source file db/add_sub_u5c.tdf
    Info: Found entity 1: add_sub_u5c
Info: Duplicate registers merged to single register
    Info: Duplicate register lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|dffpipe_er2:ws_bwp|dffe4a[4] merged to single register lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|delayed_wrptr_g[4]
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: bit_cnt:inst7|bit_counter[0]~0
Info: Found 1 design units, including 1 entities, in source file d:/altera/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_vo7.tdf
    Info: Found entity 1: cntr_vo7
Info: Resynthesizing 0 WYSIWYG logic cells and I/Os using balanced technology mapper which leaves 46 WYSIWYG logic cells and I/Os untouched
Info: Performing gate-level register retiming
Warning: Can't find clock settings clk3 in current project -- ignoring clock settings
Warning: Can't find clock settings clk3 in current project -- ignoring clock settings
Info: Not allowed to move 110 registers
    Info: Not allowed to move 4 registers because they are directly fed by input pins
    Info: Not allowed to move 3 registers because they feed output pins directly
    Info: Not allowed to move 47 registers because they are fed by registers in a different clock domain
    Info: Not allowed to move 41 registers because they feed registers in a different clock domain
    Info: Not allowed to move 15 registers because they feed clock or asynchronous control signals of other registers
Info: Quartus II software applied gate-level register retiming to 2 clock domains
    Info: Quartus II software applied gate-level register retiming to clock clk_div:inst1|clk_in: created 1 new registers, removed 1 registers, left 33 registers untouched
    Info: Quartus II software applied gate-level register retiming to clock !inst11: created 6 new registers, removed 8 registers, left 16 registers untouched
Info: Implemented 318 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 75 output pins
    Info: Implemented 205 logic cells
    Info: Implemented 32 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Mon Mar 17 10:43:03 2008
    Info: Elapsed time: 00:00:11