r_sy_d_ff.v

来自「Quartus开发环境下开发的Arinc 429总线收发器工程」· Verilog 代码 · 共 12 行

module	R_SY_D_FF	( RB, CLK, Q );
input	RB, CLK;
output	Q ;
reg	Q;

always	@( posedge CLK or negedge RB ) begin
   if (!RB) 
       Q <= 1'D0;
    else
		Q <= 1'd1;
end
endmodule