429_enc_dec.fit.rpt

Quartus开发环境下开发的Arinc 429总线收发器工程

Fitter report for 429_enc_dec
Mon Mar 17 10:43:28 2008
Version 4.1 Build 181 06/29/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Floorplan View
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. I/O Bank Usage
 11. Output Pin Load For Reported TCO
 12. Fitter Resource Utilization by Entity
 13. Delay Chain Summary
 14. Pad To Core Delay Chain Fanout
 15. Control Signals
 16. Global & Other Fast Signals
 17. Non-Global High Fan-Out Signals
 18. Fitter RAM Summary
 19. Interconnect Usage Summary
 20. LAB Logic Elements
 21. LAB-wide Signals
 22. LAB Signals Sourced
 23. LAB Signals Sourced Out
 24. LAB Distinct Inputs
 25. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+---------------------------------------------------------------------+
; Fitter Summary                                                      ;
+--------------------------+------------------------------------------+
; Fitter Status            ; Successful - Mon Mar 17 10:43:28 2008    ;
; Quartus II Version       ; 4.1 Build 181 06/29/2004 SJ Full Version ;
; Revision Name            ; 429_enc_dec                              ;
; Top-level Entity Name    ; 429_enc_dec                              ;
; Family                   ; Cyclone II                               ;
; Device                   ; EP2C5Q208C7                              ;
; Timing Models            ; Preliminary                              ;
; Total logic elements     ; 192 / 4,608 ( 4 % )                      ;
; Total pins               ; 81 / 142 ( 57 % )                        ;
; Total memory bits        ; 1,024 / 119,808 ( < 1 % )                ;
; DSP block 9-bit elements ; 0 / 26 ( 0 % )                           ;
; Total PLLs               ; 0 / 2 ( 0 % )                            ;
+--------------------------+------------------------------------------+


+------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                      ;
+------------------------------------------------+--------------------+--------------------------------+
; Option                                         ; Setting            ; Default Value                  ;
+------------------------------------------------+--------------------+--------------------------------+
; Device                                         ; EP2C5Q208C7        ;                                ;
; Optimize Hold Timing                           ; All paths          ; IO Paths and Minimum TPD Paths ;
; Fitter Initial Placement Seed                  ; 2                  ; 1                              ;
; Optimize Timing                                ; Normal compilation ; Normal compilation             ;
; Optimize IOC Register Placement for Timing     ; On                 ; On                             ;
; Limit to One Fitting Attempt                   ; Off                ; Off                            ;
; Final Placement Optimizations                  ; Automatically      ; Automatically                  ;
; PCI I/O                                        ; Off                ; Off                            ;
; Weak Pull-Up Resistor                          ; Off                ; Off                            ;
; Enable Bus-Hold Circuitry                      ; Off                ; Off                            ;
; Auto Global Memory Control Signals             ; Off                ; Off                            ;
; Auto Packed Registers -- Stratix II/Cyclone II ; Auto               ; Auto                           ;
; Auto Delay Chains                              ; On                 ; On                             ;
; Auto Global Clock                              ; On                 ; On                             ;
; Auto Global Register Control Signals           ; On                 ; On                             ;
+------------------------------------------------+--------------------+--------------------------------+