429_enc_dec.tan.rpt

Quartus开发环境下开发的Arinc 429总线收发器工程

partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+---------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                    ;
+-------------------------------------------------------+--------------------+------+---------+
; Option                                                ; Setting            ; From ; To      ;
+-------------------------------------------------------+--------------------+------+---------+
; Device name                                           ; EP2C5Q208C7        ;      ;         ;
; Timing Models                                         ; Preliminary        ;      ;         ;
; Number of source nodes to report per destination node ; 10                 ;      ;         ;
; Number of destination nodes to report                 ; 10                 ;      ;         ;
; Number of paths to report                             ; 200                ;      ;         ;
; Run Minimum Analysis                                  ; On                 ;      ;         ;
; Use Minimum Timing Models                             ; Off                ;      ;         ;
; Report IO Paths Separately                            ; Off                ;      ;         ;
; Clock Analysis Only                                   ; Off                ;      ;         ;
; Default hold multicycle                               ; Same as Multicycle ;      ;         ;
; Cut paths between unrelated clock domains             ; On                 ;      ;         ;
; Cut off read during write signal paths                ; On                 ;      ;         ;
; Cut off clear and preset signal paths                 ; On                 ;      ;         ;
; Cut off feedback from I/O pins                        ; On                 ;      ;         ;
; Ignore Clock Settings                                 ; Off                ;      ;         ;
; Analyze latches as synchronous elements               ; On                 ;      ;         ;
; Clock Settings                                        ; clk3               ;      ; bit_clk ;
; Clock Settings                                        ; clk1               ;      ; clk     ;
; Clock Settings                                        ; clk3               ;      ; clk_in  ;
+-------------------------------------------------------+--------------------+------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                     ;
+------------------------------+------------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack      ; Required Time                    ; Actual Time                      ; From                                                                                              ; To                                                                                                                             ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A        ; None                             ; 2.516 ns                         ; rst_n                                                                                             ; lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|a_graycounter_aq5:rdptr_g1p|power_modified_counter_values[4] ;            ; rdclk    ; 0            ;
; Worst-case tco               ; N/A        ; None                             ; 19.960 ns                        ; lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|dffpipe_er2:ws_bwp|dffe4a[0]~13 ; wrusedw[4]                                                                                                                     ; clk        ;          ; 0            ;
; Worst-case tpd               ; N/A        ; None                             ; 6.357 ns                         ; rst_n                                                                                             ; wrclk                                                                                                                          ;            ;          ; 0            ;
; Worst-case th                ; N/A        ; None                             ; 9.003 ns                         ; rst_n                                                                                             ; lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|a_graycounter_5j6:wrptr_g1p|countera0                        ;            ; clk      ; 0            ;
; Worst-case Minimum tco       ; N/A        ; None                             ; 7.533 ns                         ; lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[1]  ; q[1]                                                                                                                           ; rdclk      ;          ; 0            ;
; Worst-case Minimum tpd       ; N/A        ; None                             ; 6.357 ns                         ; rst_n                                                                                             ; wrclk                                                                                                                          ;            ;          ; 0            ;
; Clock Setup: 'clk'           ; 111.459 ns ; 8.00 MHz ( period = 125.000 ns ) ; 73.85 MHz ( period = 13.541 ns ) ; bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[1]                 ; bit_cnt:inst7|lpm_counter:bit_counter_rtl_0|cntr_vo7:auto_generated|pre_hazard[4]                                              ; clk        ; clk      ; 0            ;