429_enc_dec.tan.rpt

Quartus开发环境下开发的Arinc 429总线收发器工程

Timing Analyzer report for 429_enc_dec
Mon Mar 17 10:43:43 2008
Version 4.1 Build 181 06/29/2004 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Timing Analyzer Settings
  3. Timing Analyzer Summary
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. Clock Setup: 'rdclk'
  7. Clock Hold: 'clk'
  8. tsu
  9. tco
 10. tpd
 11. th
 12. Minimum tco
 13. Minimum tpd
 14. Ignored Timing Assignments
 15. Timing Analyzer Messages



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; Legal Notice ;
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Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction