onessfr.v

Quartus开发环境下开发的Arinc 429总线收发器工程

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.


// Generated by Quartus II Version 4.1 (Build Build 181 06/29/2004)
// Created on Fri Mar 07 07:56:28 2008

//  Module Declaration
module onessfr
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	rst_n, ones1, clk_in, ones1_data
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input   ones1;
	input   clk_in;
	input   rst_n;
	output  ones1_data;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
    reg [0:9] ones_sfr;
    wire      ones1_val;
    wire     ones1_nval;
always @(posedge clk_in or negedge rst_n) begin
   if (!rst_n ) begin   
      ones_sfr <= 10'd0 ;
   end
   else  begin 
     ones_sfr <= {ones_sfr[1:9],ones1} ;
   end
end

assign ones1_val=ones_sfr[0]&ones_sfr[1]&ones_sfr[2]& ~ones_sfr[4]& ~ones_sfr[5]& ~ones_sfr[6];
assign ones1_nval=ones_sfr[0]| ones_sfr[1]| ones_sfr[2]| ones_sfr[4]| ones_sfr[5]| ones_sfr[6];

 R_SY_D_FF d2(ones1_nval, ones1_val, ones1_data );
endmodule