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📄 429_enc_dec.fit.eqn

📁 Quartus开发环境下开发的Arinc 429总线收发器工程
💻 EQN
📖 第 1 页 / 共 5 页
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12345 
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = GLOBAL(A1L14);
V1_q_b[31]_clock_1 = GLOBAL(A1L77);
V1_q_b[31]_clock_enable_1 = U1L12;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[26] = V1_q_b[31]_PORT_B_data_out_reg[5];

--V1_q_b[27] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[27] at M4K_X23_Y8
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = GLOBAL(A1L14);
V1_q_b[31]_clock_1 = GLOBAL(A1L77);
V1_q_b[31]_clock_enable_1 = U1L12;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[27] = V1_q_b[31]_PORT_B_data_out_reg[4];

--V1_q_b[28] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[28] at M4K_X23_Y8
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = GLOBAL(A1L14);
V1_q_b[31]_clock_1 = GLOBAL(A1L77);
V1_q_b[31]_clock_enable_1 = U1L12;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[28] = V1_q_b[31]_PORT_B_data_out_reg[3];

--V1_q_b[29] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[29] at M4K_X23_Y8
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = GLOBAL(A1L14);
V1_q_b[31]_clock_1 = GLOBAL(A1L77);
V1_q_b[31]_clock_enable_1 = U1L12;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[29] = V1_q_b[31]_PORT_B_data_out_reg[2];

--V1_q_b[30] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[30] at M4K_X23_Y8
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = GLOBAL(A1L14);
V1_q_b[31]_clock_1 = GLOBAL(A1L77);
V1_q_b[31]_clock_enable_1 = U1L12;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[30] = V1_q_b[31]_PORT_B_data_out_reg[1];

--V1_q_b[0] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[0] at M4K_X23_Y8
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = GLOBAL(A1L14);
V1_q_b[31]_clock_1 = GLOBAL(A1L77);
V1_q_b[31]_clock_enable_1 = U1L12;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[0] = V1_q_b[31]_PORT_B_data_out_reg[31];

--V1_q_b[1] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[1] at M4K_X23_Y8
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = GLOBAL(A1L14);
V1_q_b[31]_clock_1 = GLOBAL(A1L77);
V1_q_b[31]_clock_enable_1 = U1L12;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[1] = V1_q_b[31]_PORT_B_data_out_reg[30];

--V1_q_b[2] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[2] at M4K_X23_Y8
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = GLOBAL(A1L14);
V1_q_b[31]_clock_1 = GLOBAL(A1L77);
V1_q_b[31]_clock_enable_1 = U1L12;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[2] = V1_q_b[31]_PORT_B_data_out_reg[29];

--V1_q_b[3] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[3] at M4K_X23_Y8
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
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