429_enc_dec.fit.eqn

Quartus开发环境下开发的Arinc 429总线收发器工程

--S1_data[10] is data_sfr:inst8|data_lath:data_lath1|data[10] at LCFF_X21_Y5_N11
S1_data[10]_D_input = S1L22;
S1_data[10] = DFFE(S1_data[10]_D_input, GLOBAL(P3L2),  ,  ,  );


--S1_data[9] is data_sfr:inst8|data_lath:data_lath1|data[9] at LCFF_X21_Y7_N11
S1_data[9]_D_input = S1L02;
S1_data[9] = DFFE(S1_data[9]_D_input, GLOBAL(P3L2),  ,  ,  );


--S1_data[8] is data_sfr:inst8|data_lath:data_lath1|data[8] at LCFF_X25_Y6_N21
S1_data[8]_D_input = S1L81;
S1_data[8] = DFFE(S1_data[8]_D_input, GLOBAL(P3L2),  ,  ,  );


--S1_data[7] is data_sfr:inst8|data_lath:data_lath1|data[7] at LCFF_X21_Y11_N25
S1_data[7]_D_input = S1L61;
S1_data[7] = DFFE(S1_data[7]_D_input, GLOBAL(P3L2),  ,  ,  );


--S1_data[6] is data_sfr:inst8|data_lath:data_lath1|data[6] at LCFF_X24_Y8_N3
S1_data[6]_sload_eqn = K1_data_out[6];
S1_data[6]_D_input = S1_data[6]_sload_eqn;
S1_data[6] = DFFE(S1_data[6]_D_input, GLOBAL(P3L2),  ,  ,  );


--S1_data[5] is data_sfr:inst8|data_lath:data_lath1|data[5] at LCFF_X21_Y6_N15
S1_data[5]_D_input = S1L31;
S1_data[5] = DFFE(S1_data[5]_D_input, GLOBAL(P3L2),  ,  ,  );


--S1_data[4] is data_sfr:inst8|data_lath:data_lath1|data[4] at LCFF_X22_Y8_N1
S1_data[4]_D_input = S1L11;
S1_data[4] = DFFE(S1_data[4]_D_input, GLOBAL(P3L2),  ,  ,  );


--S1_data[3] is data_sfr:inst8|data_lath:data_lath1|data[3] at LCFF_X21_Y9_N23
S1_data[3]_D_input = S1L9;
S1_data[3] = DFFE(S1_data[3]_D_input, GLOBAL(P3L2),  ,  ,  );


--S1_data[2] is data_sfr:inst8|data_lath:data_lath1|data[2] at LCFF_X21_Y10_N13
S1_data[2]_D_input = S1L7;
S1_data[2] = DFFE(S1_data[2]_D_input, GLOBAL(P3L2),  ,  ,  );


--S1_data[1] is data_sfr:inst8|data_lath:data_lath1|data[1] at LCFF_X22_Y9_N3
S1_data[1]_D_input = S1L5;
S1_data[1] = DFFE(S1_data[1]_D_input, GLOBAL(P3L2),  ,  ,  );


--S1_data[0] is data_sfr:inst8|data_lath:data_lath1|data[0] at LCFF_X26_Y6_N29
S1_data[0]_D_input = S1L3;
S1_data[0] = DFFE(S1_data[0]_D_input, GLOBAL(P3L2),  ,  ,  );


--V1_q_b[31] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[31] at M4K_X23_Y8
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 32, Port B Depth: 32, Port B Width: 32
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = GLOBAL(A1L14);
V1_q_b[31]_clock_1 = GLOBAL(A1L77);
V1_q_b[31]_clock_enable_1 = U1L12;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31] = V1_q_b[31]_PORT_B_data_out_reg[0];

--V1_q_b[23] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[23] at M4K_X23_Y8
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = GLOBAL(A1L14);
V1_q_b[31]_clock_1 = GLOBAL(A1L77);
V1_q_b[31]_clock_enable_1 = U1L12;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[23] = V1_q_b[31]_PORT_B_data_out_reg[8];

--V1_q_b[24] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[24] at M4K_X23_Y8
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = GLOBAL(A1L14);
V1_q_b[31]_clock_1 = GLOBAL(A1L77);
V1_q_b[31]_clock_enable_1 = U1L12;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[24] = V1_q_b[31]_PORT_B_data_out_reg[7];

--V1_q_b[25] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[25] at M4K_X23_Y8
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_read_enable = VCC;
V1_q_b[31]_PORT_B_read_enable_reg = DFFE(V1_q_b[31]_PORT_B_read_enable, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_clock_0 = GLOBAL(A1L14);
V1_q_b[31]_clock_1 = GLOBAL(A1L77);
V1_q_b[31]_clock_enable_1 = U1L12;
V1_q_b[31]_PORT_B_data_out = MEMORY(V1_q_b[31]_PORT_A_data_in_reg, , V1_q_b[31]_PORT_A_address_reg, V1_q_b[31]_PORT_B_address_reg, V1_q_b[31]_PORT_A_write_enable_reg, V1_q_b[31]_PORT_B_read_enable_reg, , , V1_q_b[31]_clock_0, V1_q_b[31]_clock_1, , V1_q_b[31]_clock_enable_1, , );
V1_q_b[31]_PORT_B_data_out_reg = DFFE(V1_q_b[31]_PORT_B_data_out, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[25] = V1_q_b[31]_PORT_B_data_out_reg[6];

--V1_q_b[26] is lpm_fifo0:inst9|dcfifo:dcfifo_component|dcfifo_vos:auto_generated|altsyncram_2hp:fifo_ram|q_b[26] at M4K_X23_Y8
V1_q_b[31]_PORT_A_data_in = BUS(S1_data[31], S1_data[30], S1_data[29], S1_data[28], S1_data[27], S1_data[26], S1_data[25], S1_data[24], S1_data[23], S1_data[22], S1_data[21], S1_data[20], S1_data[19], S1_data[18], S1_data[17], S1_data[16], S1_data[15], S1_data[14], S1_data[13], S1_data[12], S1_data[11], S1_data[10], S1_data[9], S1_data[8], S1_data[7], S1_data[6], S1_data[5], S1_data[4], S1_data[3], S1_data[2], S1_data[1], S1_data[0]);
V1_q_b[31]_PORT_A_data_in_reg = DFFE(V1_q_b[31]_PORT_A_data_in, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_A_address = BUS(U1_wrptr_g[0], U1_wrptr_g[1], U1_wrptr_g[2], U1_wrptr_g[3], U1_wrptr_g[4]);
V1_q_b[31]_PORT_A_address_reg = DFFE(V1_q_b[31]_PORT_A_address, V1_q_b[31]_clock_0, , , );
V1_q_b[31]_PORT_B_address = BUS(W1_power_modified_counter_values[0], W1_power_modified_counter_values[1], W1_power_modified_counter_values[2], W1_power_modified_counter_values[3], W1_power_modified_counter_values[4]);
V1_q_b[31]_PORT_B_address_reg = DFFE(V1_q_b[31]_PORT_B_address, V1_q_b[31]_clock_1, , , V1_q_b[31]_clock_enable_1);
V1_q_b[31]_PORT_A_write_enable = U1L42;
V1_q_b[31]_PORT_A_write_enable_reg = DFFE(V1_q_b[31]_PORT_A_write_enable, V1_q_b[31]_clock_0, , , );