i2c_to_gpio.tan.qmsg

I2C to GPIO Port expander的Verilog HDL 程序原码

{ "Info" "ITDB_TH_RESULT" "GPIO_output\[5\]~reg0 sda sclk 1.299 ns register " "Info: th for register \"GPIO_output\[5\]~reg0\" (data pin = \"sda\", clock pin = \"sclk\") is 1.299 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 3.914 ns + Longest register " "Info: + Longest clock path from clock \"sclk\" to destination register is 3.914 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns sclk 1 CLK PIN_39 32 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_39; Fanout = 32; CLK Node = 'sclk'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.632 ns) + CELL(0.574 ns) 3.914 ns GPIO_output\[5\]~reg0 2 REG LC_X4_Y4_N6 2 " "Info: 2: + IC(2.632 ns) + CELL(0.574 ns) = 3.914 ns; Loc. = LC_X4_Y4_N6; Fanout = 2; REG Node = 'GPIO_output\[5\]~reg0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.206 ns" { sclk GPIO_output[5]~reg0 } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 96 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.282 ns ( 32.75 % ) " "Info: Total cell delay = 1.282 ns ( 32.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.632 ns ( 67.25 % ) " "Info: Total interconnect delay = 2.632 ns ( 67.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { sclk GPIO_output[5]~reg0 } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { sclk {} sclk~combout {} GPIO_output[5]~reg0 {} } { 0.000ns 0.000ns 2.632ns } { 0.000ns 0.708ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.138 ns + " "Info: + Micro hold delay of destination is 0.138 ns" {  } { { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 96 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.753 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 CLK PIN_40 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_40; Fanout = 1; CLK Node = 'sda'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns sda~1 2 COMB IOC_X5_Y0_N2 12 " "Info: 2: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = IOC_X5_Y0_N2; Fanout = 12; COMB Node = 'sda~1'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.708 ns" { sda sda~1 } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(0.663 ns) 2.753 ns GPIO_output\[5\]~reg0 3 REG LC_X4_Y4_N6 2 " "Info: 3: + IC(1.382 ns) + CELL(0.663 ns) = 2.753 ns; Loc. = LC_X4_Y4_N6; Fanout = 2; REG Node = 'GPIO_output\[5\]~reg0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.045 ns" { sda~1 GPIO_output[5]~reg0 } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 96 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.371 ns ( 49.80 % ) " "Info: Total cell delay = 1.371 ns ( 49.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.382 ns ( 50.20 % ) " "Info: Total interconnect delay = 1.382 ns ( 50.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.753 ns" { sda sda~1 GPIO_output[5]~reg0 } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.753 ns" { sda {} sda~1 {} GPIO_output[5]~reg0 {} } { 0.000ns 0.000ns 1.382ns } { 0.000ns 0.708ns 0.663ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { sclk GPIO_output[5]~reg0 } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { sclk {} sclk~combout {} GPIO_output[5]~reg0 {} } { 0.000ns 0.000ns 2.632ns } { 0.000ns 0.708ns 0.574ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.753 ns" { sda sda~1 GPIO_output[5]~reg0 } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.753 ns" { sda {} sda~1 {} GPIO_output[5]~reg0 {} } { 0.000ns 0.000ns 1.382ns } { 0.000ns 0.708ns 0.663ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "116 " "Info: Allocated 116 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 22 16:52:42 2007 " "Info: Processing ended: Thu Nov 22 16:52:42 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}