i2c_to_gpio.tan.qmsg

I2C to GPIO Port expander的Verilog HDL 程序原码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sclk " "Info: Assuming node \"sclk\" is an undefined clock" {  } { { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 12 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "sclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "sda " "Info: Assuming node \"sda\" is an undefined clock" {  } { { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 11 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "sda" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sclk register read_oper register GPIO_input_reg\[7\] 103.43 MHz 9.668 ns Internal " "Info: Clock \"sclk\" has Internal fmax of 103.43 MHz between source register \"read_oper\" and destination register \"GPIO_input_reg\[7\]\" (period= 9.668 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.391 ns + Longest register register " "Info: + Longest register to register delay is 4.391 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns read_oper 1 REG LC_X3_Y2_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N4; Fanout = 6; REG Node = 'read_oper'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { read_oper } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.612 ns) + CELL(0.319 ns) 0.931 ns always5~20 2 COMB LC_X3_Y2_N3 2 " "Info: 2: + IC(0.612 ns) + CELL(0.319 ns) = 0.931 ns; Loc. = LC_X3_Y2_N3; Fanout = 2; COMB Node = 'always5~20'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.931 ns" { read_oper always5~20 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.481 ns) + CELL(0.125 ns) 2.537 ns GPIO_input_reg\[7\]~550 3 COMB LC_X7_Y3_N3 7 " "Info: 3: + IC(1.481 ns) + CELL(0.125 ns) = 2.537 ns; Loc. = LC_X7_Y3_N3; Fanout = 7; COMB Node = 'GPIO_input_reg\[7\]~550'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.606 ns" { always5~20 GPIO_input_reg[7]~550 } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.777 ns) 4.391 ns GPIO_input_reg\[7\] 4 REG LC_X6_Y2_N9 1 " "Info: 4: + IC(1.077 ns) + CELL(0.777 ns) = 4.391 ns; Loc. = LC_X6_Y2_N9; Fanout = 1; REG Node = 'GPIO_input_reg\[7\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.854 ns" { GPIO_input_reg[7]~550 GPIO_input_reg[7] } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.221 ns ( 27.81 % ) " "Info: Total cell delay = 1.221 ns ( 27.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.170 ns ( 72.19 % ) " "Info: Total interconnect delay = 3.170 ns ( 72.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "4.391 ns" { read_oper always5~20 GPIO_input_reg[7]~550 GPIO_input_reg[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "4.391 ns" { read_oper {} always5~20 {} GPIO_input_reg[7]~550 {} GPIO_input_reg[7] {} } { 0.000ns 0.612ns 1.481ns 1.077ns } { 0.000ns 0.319ns 0.125ns 0.777ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 3.914 ns + Shortest register " "Info: + Shortest clock path from clock \"sclk\" to destination register is 3.914 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns sclk 1 CLK PIN_39 32 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_39; Fanout = 32; CLK Node = 'sclk'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.632 ns) + CELL(0.574 ns) 3.914 ns GPIO_input_reg\[7\] 2 REG LC_X6_Y2_N9 1 " "Info: 2: + IC(2.632 ns) + CELL(0.574 ns) = 3.914 ns; Loc. = LC_X6_Y2_N9; Fanout = 1; REG Node = 'GPIO_input_reg\[7\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.206 ns" { sclk GPIO_input_reg[7] } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.282 ns ( 32.75 % ) " "Info: Total cell delay = 1.282 ns ( 32.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.632 ns ( 67.25 % ) " "Info: Total interconnect delay = 2.632 ns ( 67.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { sclk GPIO_input_reg[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { sclk {} sclk~combout {} GPIO_input_reg[7] {} } { 0.000ns 0.000ns 2.632ns } { 0.000ns 0.708ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk source 3.914 ns - Longest register " "Info: - Longest clock path from clock \"sclk\" to source register is 3.914 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns sclk 1 CLK PIN_39 32 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_39; Fanout = 32; CLK Node = 'sclk'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.632 ns) + CELL(0.574 ns) 3.914 ns read_oper 2 REG LC_X3_Y2_N4 6 " "Info: 2: + IC(2.632 ns) + CELL(0.574 ns) = 3.914 ns; Loc. = LC_X3_Y2_N4; Fanout = 6; REG Node = 'read_oper'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.206 ns" { sclk read_oper } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.282 ns ( 32.75 % ) " "Info: Total cell delay = 1.282 ns ( 32.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.632 ns ( 67.25 % ) " "Info: Total interconnect delay = 2.632 ns ( 67.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { sclk read_oper } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { sclk {} sclk~combout {} read_oper {} } { 0.000ns 0.000ns 2.632ns } { 0.000ns 0.708ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { sclk GPIO_input_reg[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { sclk {} sclk~combout {} GPIO_input_reg[7] {} } { 0.000ns 0.000ns 2.632ns } { 0.000ns 0.708ns 0.574ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { sclk read_oper } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { sclk {} sclk~combout {} read_oper {} } { 0.000ns 0.000ns 2.632ns } { 0.000ns 0.708ns 0.574ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns + " "Info: + Micro setup delay of destination is 0.208 ns" {  } { { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 162 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 30 -1 0 } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 162 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "4.391 ns" { read_oper always5~20 GPIO_input_reg[7]~550 GPIO_input_reg[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "4.391 ns" { read_oper {} always5~20 {} GPIO_input_reg[7]~550 {} GPIO_input_reg[7] {} } { 0.000ns 0.612ns 1.481ns 1.077ns } { 0.000ns 0.319ns 0.125ns 0.777ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { sclk GPIO_input_reg[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { sclk {} sclk~combout {} GPIO_input_reg[7] {} } { 0.000ns 0.000ns 2.632ns } { 0.000ns 0.708ns 0.574ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { sclk read_oper } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { sclk {} sclk~combout {} read_oper {} } { 0.000ns 0.000ns 2.632ns } { 0.000ns 0.708ns 0.574ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "sda " "Info: No valid register-to-register data paths exist for clock \"sda\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "add_is_matching sda sclk 0.490 ns register " "Info: tsu for register \"add_is_matching\" (data pin = \"sda\", clock pin = \"sclk\") is 0.490 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.196 ns + Longest pin register " "Info: + Longest pin to register delay is 4.196 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 CLK PIN_40 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_40; Fanout = 1; CLK Node = 'sda'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns sda~1 2 COMB IOC_X5_Y0_N2 12 " "Info: 2: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = IOC_X5_Y0_N2; Fanout = 12; COMB Node = 'sda~1'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.708 ns" { sda sda~1 } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.397 ns) + CELL(0.571 ns) 2.676 ns add_is_matching~172 3 COMB LC_X4_Y3_N7 1 " "Info: 3: + IC(1.397 ns) + CELL(0.571 ns) = 2.676 ns; Loc. = LC_X4_Y3_N7; Fanout = 1; COMB Node = 'add_is_matching~172'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.968 ns" { sda~1 add_is_matching~172 } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.319 ns) 3.493 ns add_is_matching~173 4 COMB LC_X4_Y3_N4 1 " "Info: 4: + IC(0.498 ns) + CELL(0.319 ns) = 3.493 ns; Loc. = LC_X4_Y3_N4; Fanout = 1; COMB Node = 'add_is_matching~173'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.817 ns" { add_is_matching~172 add_is_matching~173 } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.334 ns) + CELL(0.369 ns) 4.196 ns add_is_matching 5 REG LC_X4_Y3_N5 6 " "Info: 5: + IC(0.334 ns) + CELL(0.369 ns) = 4.196 ns; Loc. = LC_X4_Y3_N5; Fanout = 6; REG Node = 'add_is_matching'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.703 ns" { add_is_matching~173 add_is_matching } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.967 ns ( 46.88 % ) " "Info: Total cell delay = 1.967 ns ( 46.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.229 ns ( 53.12 % ) " "Info: Total interconnect delay = 2.229 ns ( 53.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "4.196 ns" { sda sda~1 add_is_matching~172 add_is_matching~173 add_is_matching } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "4.196 ns" { sda {} sda~1 {} add_is_matching~172 {} add_is_matching~173 {} add_is_matching {} } { 0.000ns 0.000ns 1.397ns 0.498ns 0.334ns } { 0.000ns 0.708ns 0.571ns 0.319ns 0.369ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns + " "Info: + Micro setup delay of destination is 0.208 ns" {  } { { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 3.914 ns - Shortest register " "Info: - Shortest clock path from clock \"sclk\" to destination register is 3.914 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns sclk 1 CLK PIN_39 32 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_39; Fanout = 32; CLK Node = 'sclk'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.632 ns) + CELL(0.574 ns) 3.914 ns add_is_matching 2 REG LC_X4_Y3_N5 6 " "Info: 2: + IC(2.632 ns) + CELL(0.574 ns) = 3.914 ns; Loc. = LC_X4_Y3_N5; Fanout = 6; REG Node = 'add_is_matching'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.206 ns" { sclk add_is_matching } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.282 ns ( 32.75 % ) " "Info: Total cell delay = 1.282 ns ( 32.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.632 ns ( 67.25 % ) " "Info: Total interconnect delay = 2.632 ns ( 67.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { sclk add_is_matching } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { sclk {} sclk~combout {} add_is_matching {} } { 0.000ns 0.000ns 2.632ns } { 0.000ns 0.708ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "4.196 ns" { sda sda~1 add_is_matching~172 add_is_matching~173 add_is_matching } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "4.196 ns" { sda {} sda~1 {} add_is_matching~172 {} add_is_matching~173 {} add_is_matching {} } { 0.000ns 0.000ns 1.397ns 0.498ns 0.334ns } { 0.000ns 0.708ns 0.571ns 0.319ns 0.369ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { sclk add_is_matching } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { sclk {} sclk~combout {} add_is_matching {} } { 0.000ns 0.000ns 2.632ns } { 0.000ns 0.708ns 0.574ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sclk GPIO_output\[7\] GPIO_output\[7\]~reg0 7.178 ns register " "Info: tco from clock \"sclk\" to destination pin \"GPIO_output\[7\]\" through register \"GPIO_output\[7\]~reg0\" is 7.178 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk source 3.914 ns + Longest register " "Info: + Longest clock path from clock \"sclk\" to source register is 3.914 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns sclk 1 CLK PIN_39 32 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_39; Fanout = 32; CLK Node = 'sclk'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.632 ns) + CELL(0.574 ns) 3.914 ns GPIO_output\[7\]~reg0 2 REG LC_X3_Y3_N8 2 " "Info: 2: + IC(2.632 ns) + CELL(0.574 ns) = 3.914 ns; Loc. = LC_X3_Y3_N8; Fanout = 2; REG Node = 'GPIO_output\[7\]~reg0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.206 ns" { sclk GPIO_output[7]~reg0 } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 96 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.282 ns ( 32.75 % ) " "Info: Total cell delay = 1.282 ns ( 32.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.632 ns ( 67.25 % ) " "Info: Total interconnect delay = 2.632 ns ( 67.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { sclk GPIO_output[7]~reg0 } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { sclk {} sclk~combout {} GPIO_output[7]~reg0 {} } { 0.000ns 0.000ns 2.632ns } { 0.000ns 0.708ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 96 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.029 ns + Longest register pin " "Info: + Longest register to pin delay is 3.029 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns GPIO_output\[7\]~reg0 1 REG LC_X3_Y3_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y3_N8; Fanout = 2; REG Node = 'GPIO_output\[7\]~reg0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_output[7]~reg0 } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 96 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.575 ns) + CELL(1.454 ns) 3.029 ns GPIO_output\[7\] 2 PIN PIN_76 0 " "Info: 2: + IC(1.575 ns) + CELL(1.454 ns) = 3.029 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'GPIO_output\[7\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.029 ns" { GPIO_output[7]~reg0 GPIO_output[7] } "NODE_NAME" } } { "I2C_to_GPIO.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN494/quartus/I2C_to_GPIO.v" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns ( 48.00 % ) " "Info: Total cell delay = 1.454 ns ( 48.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.575 ns ( 52.00 % ) " "Info: Total interconnect delay = 1.575 ns ( 52.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.029 ns" { GPIO_output[7]~reg0 GPIO_output[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.029 ns" { GPIO_output[7]~reg0 {} GPIO_output[7] {} } { 0.000ns 1.575ns } { 0.000ns 1.454ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { sclk GPIO_output[7]~reg0 } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { sclk {} sclk~combout {} GPIO_output[7]~reg0 {} } { 0.000ns 0.000ns 2.632ns } { 0.000ns 0.708ns 0.574ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.029 ns" { GPIO_output[7]~reg0 GPIO_output[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.029 ns" { GPIO_output[7]~reg0 {} GPIO_output[7] {} } { 0.000ns 1.575ns } { 0.000ns 1.454ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}