i2c_to_gpio.fit.rpt

I2C to GPIO Port expander的Verilog HDL 程序原码

+--------------------------------------------------------------------------------+-----------------+
; Name                                                                           ; Value           ;
+--------------------------------------------------------------------------------+-----------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff              ;
; Mid Wire Use - Fit Attempt 1                                                   ; 16              ;
; Mid Slack - Fit Attempt 1                                                      ; -7045           ;
; Internal Atom Count - Fit Attempt 1                                            ; 61              ;
; LE/ALM Count - Fit Attempt 1                                                   ; 61              ;
; LAB Count - Fit Attempt 1                                                      ; 10              ;
; Outputs per Lab - Fit Attempt 1                                                ; 4.300           ;
; Inputs per LAB - Fit Attempt 1                                                 ; 8.600           ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.600           ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:10            ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:4;1:3;2:3     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:2;1:5;2:3     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:2;1:5;2:3     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:2;1:3;2:5     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:2;1:3;2:5     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:8;1:2         ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:10            ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:4;1:4;2:2     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1;1:3;2:5;3:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:3;2:6     ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:10            ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:8;2:1     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:6;1:4         ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:2;1:8         ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:10            ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:10            ;
; LEs in Chains - Fit Attempt 1                                                  ; 0               ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0               ;
; LABs with Chains - Fit Attempt 1                                               ; 0               ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0               ;
; Time - Fit Attempt 1                                                           ; 0               ;
+--------------------------------------------------------------------------------+-----------------+


+--------------------------------------------+
; Advanced Data - Placement                  ;
+------------------------------------+-------+
; Name                               ; Value ;
+------------------------------------+-------+
; Auto Fit Point 2 - Fit Attempt 1   ; ff    ;
; Early Wire Use - Fit Attempt 1     ; 4     ;
; Early Slack - Fit Attempt 1        ; -7608 ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff    ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff    ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff    ;
; Mid Wire Use - Fit Attempt 1       ; 8     ;
; Mid Slack - Fit Attempt 1          ; -7285 ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff    ;
; Late Wire Use - Fit Attempt 1      ; 9     ;
; Late Slack - Fit Attempt 1         ; -7285 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff    ;
; Time - Fit Attempt 1               ; 0     ;
+------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; -6667 ;
; Early Wire Use - Fit Attempt 1      ; 8     ;
; Peak Regional Wire - Fit Attempt 1  ; 7     ;
; Mid Slack - Fit Attempt 1           ; -6688 ;
; Late Slack - Fit Attempt 1          ; -6688 ;
; Late Wire Use - Fit Attempt 1       ; 9     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;
+-------------------------------------+-------+


+----------------------------------------------------------------+
; Fitter INI Usage                                               ;
+----------------------+-----------------------------------------+
; Option               ; Usage                                   ;
+----------------------+-----------------------------------------+
; Initialization file: ; c:/altera/72_cc/quartus/bin/quartus.ini ;
; debug_msg            ; OFF                                     ;
+----------------------+-----------------------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Nov 22 16:52:32 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off I2C_to_GPIO -c I2C_to_GPIO
Info: Selected device EPM240GT100C3 for design "I2C_to_GPIO"
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570GT100C3 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted some destinations of signal "sclk" to use Global clock
    Info: Destination "start" may be non-global or may not use global clock
    Info: Destination "stop" may be non-global or may not use global clock
Info: Pin "sclk" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted some destinations of signal "sda" to use Global clock
    Info: Destination "GPIO_output[0]~reg0" may be non-global or may not use global clock
    Info: Destination "GPIO_output[1]~reg0" may be non-global or may not use global clock
    Info: Destination "GPIO_output[2]~reg0" may be non-global or may not use global clock
    Info: Destination "GPIO_output[3]~reg0" may be non-global or may not use global clock
    Info: Destination "GPIO_output[4]~reg0" may be non-global or may not use global clock
    Info: Destination "GPIO_output[5]~reg0" may be non-global or may not use global clock
    Info: Destination "GPIO_output[6]~reg0" may be non-global or may not use global clock
    Info: Destination "GPIO_output[7]~reg0" may be non-global or may not use global clock
    Info: Destination "read_oper" may be non-global or may not use global clock
    Info: Destination "add_is_matching~172" may be non-global or may not use global clock
Info: Pin "sda~1" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted some destinations of signal "reset" to use Global clock
    Info: Destination "reset" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 2.928 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y3; Fanout = 2; REG Node = 'GPIO_output[7]~reg0'
    Info: 2: + IC(1.474 ns) + CELL(1.454 ns) = 2.928 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'GPIO_output[7]'
    Info: Total cell delay = 1.454 ns ( 49.66 % )
    Info: Total interconnect delay = 1.474 ns ( 50.34 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 7% of the available device resources
    Info: Peak interconnect usage is 7% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Following groups of pins have the same output enable
    Info: Following pins have the same output enable: sda_out~en
        Info: Type bidirectional pin sda us