mx1_spi.h

车载信息系统开发源码

/*
 * mx1_spi.h
 * Define the register structure for the Serial Peripheral Interface
 * Date	: 2004/04/22
 * By	: Zhang Jing
 */

#ifndef	MX1_SPI_H
#define	MX1_SPI_H

#include	"mx1.h"

#ifdef	MX1_SPI_FLAG
	#define	MX1_SPI_EXT
#else
	#define	MX1_SPI_EXT	extern
#endif

typedef struct struct_mx1_spi{
	mx1_reg	RXDATAREG;
	mx1_reg	TXDATAREG;
	mx1_reg	CONTROLREG;
	mx1_reg	INTREG;
	mx1_reg	TESTREG;
	mx1_reg	PERIODREG;
	mx1_reg	DMAREG;
	mx1_reg	RESETREG;
} T_MX1_SPI;

// Base address of SPI1 and SPI2
#define	MX1_SPI1	((T_MX1_SPI*)0xf0213000)
#define	MX1_SPI2	((T_MX1_SPI*)0xf0219000)

// Bits set and mask for Control Register
// Selects the divide value of SCLK from PERCLK2 in the PLL and Clock Control Module
#define	DATARATE_BY4			(0x0<<13)
#define	DATARATE_BY8			(0x1<<13)
#define	DATARATE_BY16			(0x2<<13)
#define	DATARATE_BY32			(0x3<<13)
#define	DATARATE_BY64			(0x4<<13)
#define	DATARATE_BY128		(0x5<<13)
#define	DATARATE_BY256		(0x6<<13)
#define	DATARATE_BY512		(0x7<<13)
// SPI_RDY control
#define	DRCTL_IGNORE			(0x0<<11)
#define	DRCTL_FALL_EDGE		(0x1<<11)
#define	DRCTL_ACTIVE_LOW		(0x2<<11)
// SPI Mode select
#define	MODE_SLAVE			(0x0<<10)
#define	MODE_MASTER			(0x1<<10)
// SPI module enable
#define	SPIEN_DISABLE			(0x0<<9)
#define	SPIEN_ENABLE			(0x1<<9)
// Exchange
#define	XCH_IDLE			(0x0<<8)
#define	XCH_INITIATE			(0x1<<8)
#define	XCH_BUSY			(0x1<<8)
// SS polarity select
#define	SSPOL_LOW			(0x0<<7)
#define	SSPOL_HIGH			(0x1<<7)
// SS wave form select
// In master mode
#define	SSCTL_STAY_LOW		(0x0<<6)
#define	SSCTL_INSERT_PULSE		(0x1<<6)
// In slave mode
#define	SSCTL_ADV_BC			(0x0<<6)
#define	SSCTL_ADV_RISING		(0x1<<6)
// Phase
#define	PHA_Phase0			(0x0<<5)
#define	PHA_Phase1			(0x1<<5)
// Polarity
#define	POL_HIGH			(0x0<<4)
#define	POL_LOW			(0x1<<4)
// Bit Count
#define	BIT_COUNT( cnt )			(((cnt)&0xf)<<0)

// Interrupt Control and Status Register
#define	INTREG_BOEN			(0x1<<15)
#define	INTREG_ROEN			(0x1<<14)
#define	INTREG_RFEN			(0x1<<13)
#define	INTREG_RHEN			(0x1<<12)
#define	INTREG_RREN			(0x1<<11)
#define	INTREG_TFEN			(0x1<<10)
#define	INTREG_THEN			(0x1<<9)
#define	INTREG_TEEN			(0x1<<8)

#define	INTREG_BO			(0x1<<7)
#define	INTREG_RO			(0x1<<6)
#define	INTREG_RF			(0x1<<5)
#define	INTREG_RH			(0x1<<4)
#define	INTREG_RR			(0x1<<3)
#define	INTREG_TF			(0x1<<2)
#define	INTREG_TH			(0x1<<1)
#define	INTREG_TE			(0x1<<0)

// Test Register
#define	LBC_DISABLE			(0x0<<14)
#define	LBC_ENABLE			(0x1<<14)

// Sample period control register
// select the clock source
#define	CSRC_BIT_CLOCK			(0x0<<15)
#define	CSRC_32K			(0x1<<15)
// set the wait clocks
#define	WAIT( cnt )			(((cnt)&0x7fff)<<0)
// DMA Control Register
#define	DMAREG_THDEN			(0x1<<15)
#define	DMAREG_TEDEN			(0x1<<14)
#define	DMAREG_RFDEN			(0x1<<13)
#define	DMAREG_RHDEN			(0x1<<12)

#define	DMAREG_THDMA			(0x1<<7)
#define	DMAREG_TEDMA			(0x1<<6)
#define	DMAREG_RFDMA			(0x1<<5)
#define	DMAREG_RHDMA			(0x1<<4)
// Software Reset register
#define	RESETREG_START		(0x1<<0)


// Function prototypes
MX1_SPI_EXT void MX1_SPI_Init(T_MX1_SPI * spi_module);
MX1_SPI_EXT void MX1_SPI_TXFlush(T_MX1_SPI * spi_module);
MX1_SPI_EXT void MX1_SPI_RXFlush(T_MX1_SPI * spi_module);
MX1_SPI_EXT void MX1_SPI_Send(T_MX1_SPI * spi_module, unsigned int data);
MX1_SPI_EXT unsigned int MX1_SPI_Recv(T_MX1_SPI * spi_module);

#endif