mx1_def.h

车载信息系统开发源码

/******************************************************************************

 C   H E A D E R   F I L E

 (c) Copyright Motorola Semiconductors Hong Kong Limited 2001-2002
 ALL RIGHTS RESERVED

*******************************************************************************

 Project Name : DBMX1 System Test Program
 Project No.  : 
 Title        : 
 Template Ver : 0.3
 File Name    : MX1_def.h  
 Last Modified: Nov 14, 2001

 Description  : Definition header for DBMX1 silicon. 

 Assumptions  : NA
 
 Dependency Comments : NA

 Project Specific Data : NA

******************************************************************************/
#ifndef MX1_DEF_INC
#define MX1_DEF_INC

/*************************** Header File Includes ****************************/
/********************************* Constants *********************************/
/******************************** Enumeration ********************************/
/****************************** Basic Data types *****************************/
/************************* Structure/Union Data types ************************/
/********************************** Macros ***********************************/

/* common define for MX1 */
//$0000 0000 - $000F FFFF Double Map Image 1 MB
//$0010 0000 - $001F FFFF Bootstrap ROM 1 MB
//$0020 0000 - $0020 0FFF AIPI1 4 KB
//$0020 1000 - $0020 1FFF WatchDog 4 KB
//$0020 2000 - $0020 2FFF TIMER1 4 KB
//$0020 3000 - $0020 3FFF TIMER2 4 KB
//$0020 4000 - $0020 4FFF RTC 4 KB
//$0020 5000 - $0020 5FFF LCD 4 KB
//$0020 6000 - $0020 6FFF UART1 4 KB
//$0020 7000 - $0020 7FFF UART2 4 KB
//$0020 8000 - $0020 8FFF PWM 4 KB
//$0020 9000 - $0020 9FFF DMA 4 KB
//$0020 A000 - $0020 AFFF Reserved 4 KB
//$0020 B000 - $0020 BFFF Reserved 4 KB
//$0020 C000 - $0020 CFFF Reserved 4 KB
//$0020 D000 - $0020 DFFF Reserved 4 KB
//$0020 E000 - $0020 EFFF Reserved 4 KB
//$0020 F000 - $0020 FFFF Reserved 4 KB
//$0021 0000 - $0021 0FFF AIPI2 4 KB
//$0021 1000 - $0021 1FFF SIM 4 KB
//$0021 2000 - $0021 2FFF USBD 4 KB
//$0021 3000 - $0021 3FFF CSPI 4 KB
//$0021 4000 - $0021 4FFF MMC 4 KB
//$0021 5000 - $0021 5FFF ASP 4 KB
//$0021 6000 - $0021 6FFF BTA 4 KB
//$0021 7000 - $0021 7FFF I2C 4 KB
//$0021 8000 - $0021 8FFF SSI 4 KB
//$0021 9000 - $0021 9FFF Reserved 4 KB
//$0021 A000 - $ 0021 AFFF Memory Stick 4 KB
//$0021 B000 - $0021 BFFF CRM 4 KB
//$0021 C000 - $ 0021 CFFF GPIO 4 KB
//$0021 D000 - $0021 DFFF Reserved 4 KB
//$0021 E000 - $0021 EFFF Reserved 4 KB
//$0021 F000 - $0021 FFFF Reserved 4 KB
//$0022 0000 - $0022 0FFF WEIM 4 KB
//$0022 1000 - $0022 1FFF SDRAMC 4 KB
//$0022 2000 - $0022 2FFF DSPA 4 KB
//$0022 3000 - $0022 3FFF AITC 4 KB
//$0022 4000 - $0022 4FFF CSI 4 KB
//$0022 5000 - $0022 5FFF Reserved 4 KB
//$0022 6000 - $0022 6FFF Reserved 4 KB
//$0022 7000 - $002F FFFF Reserved 868 KB

// ; Memory Map
// ; ----------
// ; $0020_0XXX aipi1
// ; $0020_1XXX Watchdog (wdt_ip)
// ; $0020_2XXX Timer1 (timer_ip1)
// ; $0020_3XXX Timer2 (timer_ip2)
// ; $0020_4XXX RTC (rtc_ip)
// ; $0020_5XXX LCD (lcd_ip)
// ; $0020_6XXX UART1 (uart_ip1)
// ; $0020_7XXX UART2 (uart_ip2)
// ; $0020_8XXX PWM (pwm_ip)
// ; $0020_9XXX DMA (dma_ip)
// ; $0020_AXXX Reserved
// ; $0020_BXXX Reserved
// ; $0020_CXXX Reserved
// ; $0020_DXXX Reserved
// ; $0020_EXXX Reserved
// ; $0020_FXXX Reserved
// ; 
// ; $0021_0XXX AIPI2 (dbmx_aipi2)
// ; $0021_1XXX SIM (sim_ip)
// ; $0021_2XXX USBD (usbd_ip)
// ; $0021_3XXX CSPI (cspi_ip)
// ; $0021_4XXX MMC (mmc_ip)
// ; $0021_5XXX ASP (asp_ip)
// ; $0021_6XXX BTA (bta_ip)
// ; $0021_7XXX I2C (i2c)
// ; $0021_8XXX SSI (ssi_ip)
// ; $0021_9XXX Video Port
// ; $0021_AXXX Memory Stick
// ; $0021_BXXX Clock & Reset (crm)
// ; $0021_CXXX GPIO (gpio_ip)
// ; $0021_DXXX Reserved
// ; $0021_EXXX Reserved
// ; $0021_FXXX Reserved
// ;
// ; $0022_0XXX Weim
// ; $0022_1XXX SDRAMC
// ; $0022_2XXX DSPA
// ; $0022_3XXX AITC
// ; $0022_4XXX Ext1
// ; $0022_5XXX Ext2
// ; $0022_6XXX Ext3

// ; ARM Program Status Register
// ;  31  30  29  28  27             7   6   5  4
// ; ----------------------------------------------------------
// ; | N | Z | C | V | Q |         | I | F | T |  |  |  |  |  |
// ; ----------------------------------------------------------
//
// ;---------------------------------------;
// ;ARM modes                              ;
// ;---------------------------------------;
#define MODE_USR                0x10
#define MODE_FIQ                0x11
#define MODE_IRQ                0x12
#define MODE_SVC                0x13
#define MODE_ABT                0x17
#define MODE_UND                0x1B
#define MODE_SYS                0x1F
#define MODE_BITS               0x1F
#define TBIT                    (1:SHL:5)
#define FBIT                    (1:SHL:6)
#define IBIT                    (1:SHL:7)
//
// ;---------------------------------------;
// ; ARM interrupts                        ;
// ;---------------------------------------;
#define INTERRUPT_BITS          0xC0
#define ENABLE_IRQ              0x0
#define ENABLE_FIQ              0x0
#define DISABLE_FIQ             0x40
#define DISABLE_IRQ             0x80
//
// ;---------------------------------------;
// ; ARM FLAGS                             ;
// ;---------------------------------------;
#define FLAG_BITS               0xF0000000
#define NFLAG                   0x80000000
#define ZFLAG                   0x40000000
#define CFLAG                   0x20000000
#define VFLAG                   0x10000000
//
// ;---------------------------------------;
// ; STACK                                 ;
// ;---------------------------------------;
#define SVC_STACK               TOP_OF_STACK            // ; 003F_FDFF - 0040_0000 (512B)
#define IRQ_STACK               (TOP_OF_STACK-0x200)    // ; 003F_FBFF - 003F_FE00 (512B)
#define FIQ_STACK               (TOP_OF_STACK-0x400)    // ; 003F_F9FF - 003F_FC00 (512B)
#define USR_STACK               (TOP_OF_STACK-0x600)    // ; 003F_F7FF - 003F_FA00 (512B)
#define UND_STACK               (TOP_OF_STACK-0x800)    // ; 003F_F7FF - 003F_FA00 (512B)

// ;---------------------------------------;
// ; AIPI1                                 ;
// ; $0020_0000 to $0020_0FFF              ;
// ;---------------------------------------;
#define AIPI1_BASE_ADDR         0x00200000              // ; Peripheral Size Reg 0
#define AIPI1_PSR0              AIPI1_BASE_ADDR        // ; Peripheral Size Reg 1
#define AIPI1_PSR1              (AIPI1_BASE_ADDR+0x04)
#define AIPI1_PAR               (AIPI1_BASE_ADDR+0x08)  // ; Peripheral Access Reg
//
// ;---------------------------------------;
// ; AIPI2                                 ;
// ; $0021_0000 to $0021_0FFF              ;
// ;---------------------------------------;
#define AIPI2_BASE_ADDR         0x00210000             
#define AIPI2_PSR0              AIPI2_BASE_ADDR        // ; Peripheral Size Reg 0
#define AIPI2_PSR1              (AIPI2_BASE_ADDR+0x04)  // ; Peripheral Size Reg 1
#define AIPI2_PAR               (AIPI2_BASE_ADDR+0x08)  // ; Peripheral Access Reg
//
// ;---------------------------------------; 
// ; PLL Clock                             ;
// ; $0021_B000 to $0021_B020              ;
// ;---------------------------------------; 
//
/* Register base address */
#define PLL_BASE                0x0021B000
//
/* Reset Module*/
#define PLL_CSCR                (PLL_BASE+0x00) //Clock Source Control Register
#define PLL_PCDR                (PLL_BASE+0x20) //Peripherial Clock Divider Register
/* PLL & Clock Controller */
#define PLL_MCTL0               (PLL_BASE+0x04) //MCU PLL Control Register 0
#define PLL_MCTL1               (PLL_BASE+0x08) //MCU PLL Control Register 1
#define PLL_UPCTL0              (PLL_BASE+0x0C) //USB PLL Control Register 0
#define PLL_UPCTL1              (PLL_BASE+0x10) //USB PLL Control Register 1

#define UPLL_RESTART			0x00400000      
#define MPLL_RESTART			0x00200000
#define CLK16_SEL_RFBTCLK16		0x00040000
#define OSC_EN					0x00020000
#define USB_SEL_EXTERNAL16      0x00010000
#define PRESC_2					0x00008000
#define UPEN					0x00000002
#define MPEN					0x00000001					

/* System Control */
#define PLL_RSR                 (PLL_BASE+0x800) //Reset Source Register
#define PLL_SIDR                (PLL_BASE+0x804) //Silicon ID Register
#define PLL_FMCR                (PLL_BASE+0x808) //Function Muxing Control Register
#define PLL_GPCR                (PLL_BASE+0x80C) //Global Peripherial Control Regiser
// ;---------------------------------------;
// ; AITC                                  ;
// ; $0022_3000 to $0022_3FFF              ;
// ;---------------------------------------;

#define AITC_BASE_ADDR          0x00223000
#define AITC_INTCNTL            (AITC_BASE_ADDR+0x00) //Interrupt Control Register
#define AITC_NIMASK             (AITC_BASE_ADDR+0x04) //Normal Interrupt Mask Register
#define AITC_INTENNUM           (AITC_BASE_ADDR+0x08) //Interrupt Enable Number Register
#define AITC_INTDISNUM          (AITC_BASE_ADDR+0x0C) //Interrupt Disable Number Register
#define AITC_INTENABLEH         (AITC_BASE_ADDR+0x10) //Interrupt Enable Register High
#define AITC_INTENABLEL         (AITC_BASE_ADDR+0x14) //Interrupt Enable Register Low
#define AITC_INTTYPEH           (AITC_BASE_ADDR+0x18)
#define AITC_INTTYPEL           (AITC_BASE_ADDR+0x1C)
#define AITC_NIPRIORITY7        (AITC_BASE_ADDR+0x20)
#define AITC_NIPRIORITY6        (AITC_BASE_ADDR+0x24)
#define AITC_NIPRIORITY5        (AITC_BASE_ADDR+0x28)
#define AITC_NIPRIORITY4        (AITC_BASE_ADDR+0x2C)
#define AITC_NIPRIORITY3        (AITC_BASE_ADDR+0x30)
#define AITC_NIPRIORITY2        (AITC_BASE_ADDR+0x34)
#define AITC_NIPRIORITY1        (AITC_BASE_ADDR+0x38)
#define AITC_NIPRIORITY0        (AITC_BASE_ADDR+0x3C)
#define AITC_NIVECSR            (AITC_BASE_ADDR+0x40)
#define AITC_FIVECSR            (AITC_BASE_ADDR+0x44)
#define AITC_INTSRCH            (AITC_BASE_ADDR+0x48)
#define AITC_INTSRCL            (AITC_BASE_ADDR+0x4C)