vhdlthreelinespi.txt

ＳＰＩ总线与ＣＰＬＤ之间的通信程序

说明:该段代码为三线制SPI接口(CS,SDA,SCK)的源码,像一般的AD或者DA器件或者时钟芯片如DS1302采用的都是这种接口.本段代码是我的的一个系统中的一个接口部分,功能比较简单,实现的功能是通过12个SCK完成一次数据的设定.经过仿真和下载测试.用户可以在此基础上修改增加其他的功能.

声明:该代码为个人原创,若要转载请注明出处.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity sig_new is
 port(
   SCK,SDA,CS : in std_logic;
   data : out std_logic_vector(11 downto 0);
   counter2 : buffer std_logic_vector(3 downto 0);
   counter1 : out std_logic_vector(3 downto 0)
  );
end entity;

architecture behavior of sig_new is
signal datatemp : std_logic_vector(11 downto 0);
signal counter : std_logic_vector(3 downto 0);
begin

P1: process ( SCK,CS )
 begin
  if SCK'event and SCK = '1' then
   if CS = '0' then
    if counter < "1100" then
     counter <= counter + 1;
     counter2 <= counter;
     for i in 0 to 10 loop
      datatemp(11-i) <= datatemp(10-i);
     end loop;
     datatemp(0) <= SDA;
    end if;
   end if;
  end if;

  if CS = '1' and CS'LAST_VALUE = '0' then
   if counter2 = "1011" then
    data <= datatemp;
   end if;
   counter <= "0000" ;
  end if;
 end process;

 counter1 <= counter;
 
end architecture;