📄 vsprintf.c.s
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; generated by ARM C Compiler, ADS1.2 [Build 805]
; commandline [-O0 -browseinfo "0xff
" -S -g+ -apcs /interwork -fk -J:cw:]
CODE32
AREA ||.text||, CODE, READONLY
skip_atoi PROC
MOV r1,r0
MOV r0,#0
NOP
|L1.12|
LDR r2,[r1,#0]
LDRB r2,[r2,#0]
SUB r2,r2,#0x30
CMP r2,#9
BHI |L1.60|
LDR r2,[r1,#0]
LDRB r3,[r2],#1
STR r2,[r1,#0]
ADD r2,r0,r0,LSL #2
ADD r2,r3,r2,LSL #1
SUB r0,r2,#0x30
B |L1.12|
|L1.60|
BX lr
ENDP
number PROC
STMFD sp!,{r4-r11,lr}
SUB sp,sp,#0x34
MOV r4,r0
MOV r8,r1
MOV r9,r2
MOV r5,r3
LDR r6,[sp,#0x5c]
LDR r10,[sp,#0x58]
ADR r0,|L1.692|
STR r0,[sp,#8]
TST r6,#0x40
BEQ |L1.120|
ADR r0,|L1.732|
STR r0,[sp,#8]
|L1.120|
TST r6,#0x10
BEQ |L1.132|
BIC r6,r6,#1
|L1.132|
CMP r9,#2
BLT |L1.148|
CMP r9,#0x24
BLE |L1.164|
|L1.148|
MOV r0,#0
|L1.152|
ADD sp,sp,#0x34
LDMFD sp!,{r4-r11,lr}
BX lr
|L1.164|
TST r6,#1
BEQ |L1.180|
MOV r0,#0x30
B |L1.184|
|L1.180|
MOV r0,#0x20
|L1.184|
AND r0,r0,#0xff
STR r0,[sp,#0x30]
TST r6,#2
BEQ |L1.220|
CMP r8,#0
BGE |L1.220|
MOV r11,#0x2d
RSB r8,r8,#0
B |L1.260|
|L1.220|
TST r6,#4
BEQ |L1.236|
MOV r0,#0x2b
B |L1.256|
|L1.236|
TST r6,#8
BEQ |L1.252|
MOV r0,#0x20
B |L1.256|
|L1.252|
MOV r0,#0
|L1.256|
AND r11,r0,#0xff
|L1.260|
CMP r11,#0
BEQ |L1.272|
SUB r5,r5,#1
|L1.272|
TST r6,#0x20
BEQ |L1.308|
CMP r9,#0x10
BNE |L1.296|
SUB r5,r5,#2
B |L1.308|
|L1.296|
CMP r9,#8
BNE |L1.308|
SUB r5,r5,#1
|L1.308|
MOV r7,#0
CMP r8,#0
BNE |L1.344|
MOV r2,#0x30
MOV r0,r7
ADD r7,r7,#1
ADD r1,sp,#0xc
STRB r2,[r1,r0]
B |L1.420|
|L1.344|
NOP
|L1.348|
CMP r8,#0
BEQ |L1.420|
NOP
MOV r1,r8
MOV r0,r9
BL __rt_sdiv
STR r1,[sp,#4]
MOV r1,r8
MOV r0,r9
BL __rt_sdiv
MOV r8,r0
LDMIB sp,{r0,r1}
LDRB r2,[r1,r0]
MOV r0,r7
ADD r7,r7,#1
ADD r1,sp,#0xc
STRB r2,[r1,r0]
B |L1.348|
|L1.420|
CMP r7,r10
BLE |L1.432|
MOV r10,r7
|L1.432|
SUB r5,r5,r10
TST r6,#0x11
BNE |L1.476|
NOP
|L1.448|
MOV r0,r5
SUB r5,r5,#1
CMP r0,#0
BLE |L1.476|
MOV r0,#0x20
STRB r0,[r4],#1
B |L1.448|
|L1.476|
CMP r11,#0
BEQ |L1.488|
STRB r11,[r4],#1
|L1.488|
TST r6,#0x20
BEQ |L1.544|
CMP r9,#8
BNE |L1.516|
MOV r0,#0x30
STRB r0,[r4],#1
B |L1.544|
|L1.516|
CMP r9,#0x10
BNE |L1.544|
MOV r0,#0x30
STRB r0,[r4],#1
LDR r1,[sp,#8]
LDRB r0,[r1,#0x21]
STRB r0,[r4],#1
|L1.544|
TST r6,#0x10
BNE |L1.584|
NOP
|L1.556|
MOV r0,r5
SUB r5,r5,#1
CMP r0,#0
BLE |L1.584|
LDR r0,[sp,#0x30]
STRB r0,[r4],#1
B |L1.556|
|L1.584|
NOP
|L1.588|
MOV r0,r10
SUB r10,r10,#1
CMP r0,r7
BLE |L1.616|
MOV r0,#0x30
STRB r0,[r4],#1
B |L1.588|
|L1.616|
NOP
|L1.620|
MOV r0,r7
SUB r7,r7,#1
CMP r0,#0
BLE |L1.652|
ADD r0,sp,#0xc
LDRB r0,[r0,r7]
STRB r0,[r4],#1
B |L1.620|
|L1.652|
NOP
|L1.656|
MOV r0,r5
SUB r5,r5,#1
CMP r0,#0
BLE |L1.684|
MOV r0,#0x20
STRB r0,[r4],#1
B |L1.656|
|L1.684|
MOV r0,r4
B |L1.152|
|L1.692|
DCB "0123"
DCB "4567"
DCB "89AB"
DCB "CDEF"
DCB "GHIJ"
DCB "KLMN"
DCB "OPQR"
DCB "STUV"
DCB "WXYZ"
DCB "\0\0\0\0"
|L1.732|
DCB "0123"
DCB "4567"
DCB "89ab"
DCB "cdef"
DCB "ghij"
DCB "klmn"
DCB "opqr"
DCB "stuv"
DCB "wxyz"
DCB "\0\0\0\0"
ENDP
vsprintf PROC
STMFD sp!,{r0-r2,r4-r11,lr}
SUB sp,sp,#0x10
MOV r5,r2
LDR r4,[sp,#0x10]
|L1.788|
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
CMP r0,#0
BEQ |L1.1900|
B |L1.824|
|L1.808|
LDR r0,[sp,#0x14]
ADD r0,r0,#1
STR r0,[sp,#0x14]
B |L1.788|
|L1.824|
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
CMP r0,#0x25
BEQ |L1.856|
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
STRB r0,[r4],#1
B |L1.808|
|L1.856|
MOV r6,#0
NOP
|L1.864|
LDR r0,[sp,#0x14]
ADD r0,r0,#1
STR r0,[sp,#0x14]
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
CMP r0,#0x2b
BEQ |L1.944|
BGT |L1.916|
CMP r0,#0x20
BEQ |L1.952|
CMP r0,#0x23
BNE |L1.976|
B |L1.960|
|L1.916|
CMP r0,#0x2d
BEQ |L1.936|
CMP r0,#0x30
BNE |L1.976|
B |L1.968|
|L1.936|
ORR r6,r6,#0x10
B |L1.864|
|L1.944|
ORR r6,r6,#4
B |L1.864|
|L1.952|
ORR r6,r6,#8
B |L1.864|
|L1.960|
ORR r6,r6,#0x20
B |L1.864|
|L1.968|
ORR r6,r6,#1
B |L1.864|
|L1.976|
MVN r7,#0
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
SUB r0,r0,#0x30
CMP r0,#9
BHI |L1.1016|
ADD r0,sp,#0x14
BL skip_atoi
MOV r7,r0
B |L1.1056|
|L1.1016|
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
CMP r0,#0x2a
BNE |L1.1056|
ADD r5,r5,#4
LDR r7,[r5,#-4]
CMP r7,#0
BGE |L1.1056|
RSB r7,r7,#0
ORR r6,r6,#0x10
|L1.1056|
MVN r8,#0
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
CMP r0,#0x2e
BNE |L1.1160|
LDR r0,[sp,#0x14]
ADD r0,r0,#1
STR r0,[sp,#0x14]
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
SUB r0,r0,#0x30
CMP r0,#9
BHI |L1.1124|
ADD r0,sp,#0x14
BL skip_atoi
MOV r8,r0
B |L1.1148|
|L1.1124|
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
CMP r0,#0x2a
BNE |L1.1148|
ADD r5,r5,#4
LDR r8,[r5,#-4]
|L1.1148|
CMP r8,#0
BGE |L1.1160|
MOV r8,#0
|L1.1160|
MVN r0,#0
STR r0,[sp,#8]
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
CMP r0,#0x68
BEQ |L1.1216|
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
CMP r0,#0x6c
BEQ |L1.1216|
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
CMP r0,#0x4c
BNE |L1.1240|
|L1.1216|
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
STR r0,[sp,#8]
LDR r0,[sp,#0x14]
ADD r0,r0,#1
STR r0,[sp,#0x14]
|L1.1240|
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
CMP r0,#0x6f
BEQ |L1.1596|
BGT |L1.1312|
CMP r0,#0x64
BEQ |L1.1740|
BGT |L1.1292|
CMP r0,#0x58
BEQ |L1.1700|
CMP r0,#0x63
BNE |L1.1824|
B |L1.1348|
|L1.1292|
CMP r0,#0x69
BEQ |L1.1744|
CMP r0,#0x6e
BNE |L1.1824|
B |L1.1792|
|L1.1312|
CMP r0,#0x70
BEQ |L1.1636|
CMP r0,#0x73
BEQ |L1.1436|
CMP r0,#0x75
BEQ |L1.1752|
CMP r0,#0x78
BNE |L1.1824|
B |L1.1692|
|L1.1348|
TST r6,#0x10
BNE |L1.1388|
NOP
|L1.1360|
SUB r0,r7,#1
MOV r7,r0
CMP r0,#0
BLE |L1.1388|
MOV r0,#0x20
STRB r0,[r4],#1
B |L1.1360|
|L1.1388|
ADD r5,r5,#4
LDR r0,[r5,#-4]
STRB r0,[r4],#1
NOP
|L1.1404|
SUB r0,r7,#1
MOV r7,r0
CMP r0,#0
BLE |L1.1432|
MOV r0,#0x20
STRB r0,[r4],#1
B |L1.1404|
|L1.1432|
B |L1.1896|
|L1.1436|
ADD r5,r5,#4
LDR r11,[r5,#-4]
MOV r0,r11
BL strlen
MOV r9,r0
CMP r8,#0
BGE |L1.1472|
MOV r8,r9
B |L1.1484|
|L1.1472|
CMP r9,r8
BLE |L1.1484|
MOV r9,r8
|L1.1484|
TST r6,#0x10
BNE |L1.1524|
NOP
|L1.1496|
MOV r0,r7
SUB r7,r7,#1
CMP r0,r9
BLE |L1.1524|
MOV r0,#0x20
STRB r0,[r4],#1
B |L1.1496|
|L1.1524|
MOV r10,#0
|L1.1528|
CMP r10,r9
BGE |L1.1560|
B |L1.1548|
|L1.1540|
ADD r10,r10,#1
B |L1.1528|
|L1.1548|
LDRB r1,[r11],#1
STRB r1,[r4],#1
B |L1.1540|
|L1.1560|
NOP
|L1.1564|
MOV r0,r7
SUB r7,r7,#1
CMP r0,r9
BLE |L1.1592|
MOV r0,#0x20
STRB r0,[r4],#1
B |L1.1564|
|L1.1592|
B |L1.1896|
|L1.1596|
ADD r5,r5,#4
STR r6,[sp,#4]
STR r8,[sp,#0]
MOV r3,r7
MOV r2,#8
MOV r0,r4
LDR r1,[r5,#-4]
BL number
MOV r4,r0
B |L1.1896|
|L1.1636|
CMN r7,#1
BNE |L1.1652|
MOV r7,#8
ORR r6,r6,#1
|L1.1652|
ADD r5,r5,#4
STR r6,[sp,#4]
STR r8,[sp,#0]
MOV r3,r7
MOV r2,#0x10
MOV r0,r4
LDR r1,[r5,#-4]
BL number
MOV r4,r0
B |L1.1896|
|L1.1692|
ORR r6,r6,#0x40
NOP
|L1.1700|
ADD r5,r5,#4
STR r6,[sp,#4]
STR r8,[sp,#0]
MOV r3,r7
MOV r2,#0x10
MOV r0,r4
LDR r1,[r5,#-4]
BL number
MOV r4,r0
B |L1.1896|
|L1.1740|
NOP
|L1.1744|
ORR r6,r6,#2
NOP
|L1.1752|
ADD r5,r5,#4
STR r6,[sp,#4]
STR r8,[sp,#0]
MOV r3,r7
MOV r2,#0xa
MOV r0,r4
LDR r1,[r5,#-4]
BL number
MOV r4,r0
B |L1.1896|
|L1.1792|
ADD r5,r5,#4
LDR r1,[r5,#-4]
STR r1,[sp,#0xc]
LDR r0,[sp,#0x10]
SUB r0,r4,r0
LDR r1,[sp,#0xc]
STR r0,[r1,#0]
B |L1.1896|
|L1.1824|
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
CMP r0,#0x25
BEQ |L1.1848|
MOV r0,#0x25
STRB r0,[r4],#1
|L1.1848|
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
CMP r0,#0
BEQ |L1.1880|
LDR r0,[sp,#0x14]
LDRB r0,[r0,#0]
STRB r0,[r4],#1
B |L1.1892|
|L1.1880|
LDR r0,[sp,#0x14]
SUB r0,r0,#1
STR r0,[sp,#0x14]
|L1.1892|
NOP
|L1.1896|
B |L1.808|
|L1.1900|
MOV r0,#0
STRB r0,[r4,#0]
LDR r0,[sp,#0x10]
SUB r0,r4,r0
ADD sp,sp,#0x1c
LDMFD sp!,{r4-r11,lr}
BX lr
ENDP
EXPORT vsprintf
IMPORT strlen
IMPORT __rt_sdiv
IMPORT ||Lib$$Request$$armlib||, WEAK
KEEP ||BuildAttributes$$THUMB_ISAv1$M$PE$A:L22$X:L11$S22$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$PRES8||
||BuildAttributes$$THUMB_ISAv1$M$PE$A:L22$X:L11$S22$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$PRES8|| EQU 0
ASSERT {ENDIAN} = "little"
ASSERT {SWST} = {FALSE}
ASSERT {NOSWST} = {TRUE}
ASSERT {INTER} = {TRUE}
ASSERT {ROPI} = {FALSE}
ASSERT {RWPI} = {FALSE}
ASSERT {NOT_SHL} = {TRUE}
ASSERT {FULL_IEEE} = {FALSE}
ASSERT {SHL1} = {FALSE}
ASSERT {SHL2} = {FALSE}
END
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