m_generate.tan.qmsg

m序列产生编码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register j\[1\] register j\[6\] 266.67 MHz 3.75 ns Internal " "Info: Clock \"clk\" has Internal fmax of 266.67 MHz between source register \"j\[1\]\" and destination register \"j\[6\]\" (period= 3.75 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.537 ns + Longest register register " "Info: + Longest register to register delay is 3.537 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns j\[1\] 1 REG LC_X71_Y41_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X71_Y41_N2; Fanout = 4; REG Node = 'j\[1\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { j[1] } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.504 ns) + CELL(0.527 ns) 1.031 ns LessThan1~93 2 COMB LC_X71_Y41_N8 1 " "Info: 2: + IC(0.504 ns) + CELL(0.527 ns) = 1.031 ns; Loc. = LC_X71_Y41_N8; Fanout = 1; COMB Node = 'LessThan1~93'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.031 ns" { j[1] LessThan1~93 } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.645 ns) + CELL(0.100 ns) 1.776 ns c~496 3 COMB LC_X72_Y41_N1 3 " "Info: 3: + IC(0.645 ns) + CELL(0.100 ns) = 1.776 ns; Loc. = LC_X72_Y41_N1; Fanout = 3; COMB Node = 'c~496'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.745 ns" { LessThan1~93 c~496 } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.159 ns) + CELL(0.100 ns) 2.035 ns Q~373 4 COMB LC_X72_Y41_N2 11 " "Info: 4: + IC(0.159 ns) + CELL(0.100 ns) = 2.035 ns; Loc. = LC_X72_Y41_N2; Fanout = 11; COMB Node = 'Q~373'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.259 ns" { c~496 Q~373 } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.603 ns) + CELL(0.899 ns) 3.537 ns j\[6\] 5 REG LC_X71_Y41_N7 2 " "Info: 5: + IC(0.603 ns) + CELL(0.899 ns) = 3.537 ns; Loc. = LC_X71_Y41_N7; Fanout = 2; REG Node = 'j\[6\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.502 ns" { Q~373 j[6] } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.626 ns ( 45.97 % ) " "Info: Total cell delay = 1.626 ns ( 45.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.911 ns ( 54.03 % ) " "Info: Total interconnect delay = 1.911 ns ( 54.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.537 ns" { j[1] LessThan1~93 c~496 Q~373 j[6] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.537 ns" { j[1] LessThan1~93 c~496 Q~373 j[6] } { 0.000ns 0.504ns 0.645ns 0.159ns 0.603ns } { 0.000ns 0.527ns 0.100ns 0.100ns 0.899ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.692 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_R3 17 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_R3; Fanout = 17; CLK Node = 'clk'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.049 ns) + CELL(0.644 ns) 3.692 ns j\[6\] 2 REG LC_X71_Y41_N7 2 " "Info: 2: + IC(2.049 ns) + CELL(0.644 ns) = 3.692 ns; Loc. = LC_X71_Y41_N7; Fanout = 2; REG Node = 'j\[6\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.693 ns" { clk j[6] } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.643 ns ( 44.50 % ) " "Info: Total cell delay = 1.643 ns ( 44.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.049 ns ( 55.50 % ) " "Info: Total interconnect delay = 2.049 ns ( 55.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.692 ns" { clk j[6] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.692 ns" { clk clk~out0 j[6] } { 0.000ns 0.000ns 2.049ns } { 0.000ns 0.999ns 0.644ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.692 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_R3 17 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_R3; Fanout = 17; CLK Node = 'clk'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.049 ns) + CELL(0.644 ns) 3.692 ns j\[1\] 2 REG LC_X71_Y41_N2 4 " "Info: 2: + IC(2.049 ns) + CELL(0.644 ns) = 3.692 ns; Loc. = LC_X71_Y41_N2; Fanout = 4; REG Node = 'j\[1\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.693 ns" { clk j[1] } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.643 ns ( 44.50 % ) " "Info: Total cell delay = 1.643 ns ( 44.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.049 ns ( 55.50 % ) " "Info: Total interconnect delay = 2.049 ns ( 55.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.692 ns" { clk j[1] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.692 ns" { clk clk~out0 j[1] } { 0.000ns 0.000ns 2.049ns } { 0.000ns 0.999ns 0.644ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.692 ns" { clk j[6] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.692 ns" { clk clk~out0 j[6] } { 0.000ns 0.000ns 2.049ns } { 0.000ns 0.999ns 0.644ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.692 ns" { clk j[1] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.692 ns" { clk clk~out0 j[1] } { 0.000ns 0.000ns 2.049ns } { 0.000ns 0.999ns 0.644ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns + " "Info: + Micro clock to output delay of source is 0.202 ns" {  } { { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.011 ns + " "Info: + Micro setup delay of destination is 0.011 ns" {  } { { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.537 ns" { j[1] LessThan1~93 c~496 Q~373 j[6] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.537 ns" { j[1] LessThan1~93 c~496 Q~373 j[6] } { 0.000ns 0.504ns 0.645ns 0.159ns 0.603ns } { 0.000ns 0.527ns 0.100ns 0.100ns 0.899ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.692 ns" { clk j[6] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.692 ns" { clk clk~out0 j[6] } { 0.000ns 0.000ns 2.049ns } { 0.000ns 0.999ns 0.644ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.692 ns" { clk j[1] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.692 ns" { clk clk~out0 j[1] } { 0.000ns 0.000ns 2.049ns } { 0.000ns 0.999ns 0.644ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Q Q~reg0 7.752 ns register " "Info: tco from clock \"clk\" to destination pin \"Q\" through register \"Q~reg0\" is 7.752 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.692 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_R3 17 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_R3; Fanout = 17; CLK Node = 'clk'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.049 ns) + CELL(0.644 ns) 3.692 ns Q~reg0 2 REG LC_X73_Y41_N4 2 " "Info: 2: + IC(2.049 ns) + CELL(0.644 ns) = 3.692 ns; Loc. = LC_X73_Y41_N4; Fanout = 2; REG Node = 'Q~reg0'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.693 ns" { clk Q~reg0 } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.643 ns ( 44.50 % ) " "Info: Total cell delay = 1.643 ns ( 44.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.049 ns ( 55.50 % ) " "Info: Total interconnect delay = 2.049 ns ( 55.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.692 ns" { clk Q~reg0 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.692 ns" { clk clk~out0 Q~reg0 } { 0.000ns 0.000ns 2.049ns } { 0.000ns 0.999ns 0.644ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns + " "Info: + Micro clock to output delay of source is 0.202 ns" {  } { { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 22 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.858 ns + Longest register pin " "Info: + Longest register to pin delay is 3.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q~reg0 1 REG LC_X73_Y41_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X73_Y41_N4; Fanout = 2; REG Node = 'Q~reg0'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q~reg0 } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.363 ns) + CELL(2.495 ns) 3.858 ns Q 2 PIN PIN_H23 0 " "Info: 2: + IC(1.363 ns) + CELL(2.495 ns) = 3.858 ns; Loc. = PIN_H23; Fanout = 0; PIN Node = 'Q'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.858 ns" { Q~reg0 Q } "NODE_NAME" } } { "M_generate.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/M_generate/M_generate.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.495 ns ( 64.67 % ) " "Info: Total cell delay = 2.495 ns ( 64.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.363 ns ( 35.33 % ) " "Info: Total interconnect delay = 1.363 ns ( 35.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.858 ns" { Q~reg0 Q } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.858 ns" { Q~reg0 Q } { 0.000ns 1.363ns } { 0.000ns 2.495ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.692 ns" { clk Q~reg0 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.692 ns" { clk clk~out0 Q~reg0 } { 0.000ns 0.000ns 2.049ns } { 0.000ns 0.999ns 0.644ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.858 ns" { Q~reg0 Q } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.858 ns" { Q~reg0 Q } { 0.000ns 1.363ns } { 0.000ns 2.495ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 20 13:05:36 2007 " "Info: Processing ended: Mon Aug 20 13:05:36 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}