m_generate.fit.smsg

m序列产生编码

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Aug 20 13:04:41 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off M_generate -c M_generate
Info: Selected device EP1S25F672C7 for design "M_generate"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1S10F672C7 is compatible
    Info: Device EP1S10F672I7 is compatible
    Info: Device EP1S20F672C7 is compatible
    Info: Device EP1S20F672I7 is compatible
    Info: Device EP1S25F672I7 is compatible
    Info: Device EP1S25F672C7_HARDCOPY_FPGA_PROTOTYPE is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
    Info: Pin ~DATA0~ is reserved at location F16
Warning: No exact pin location assignment(s) for 2 pins of 2 total pins
    Info: Pin Q not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN R3
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  60 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  59 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  54 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  55 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  59 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  61 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  57 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  54 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Estimated most critical path is register to register delay of 3.564 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X71_Y41; Fanout = 3; REG Node = 'j[3]'
    Info: 2: + IC(0.565 ns) + CELL(0.100 ns) = 0.665 ns; Loc. = LAB_X71_Y41; Fanout = 1; COMB Node = 'LessThan1~93'
    Info: 3: + IC(0.704 ns) + CELL(0.100 ns) = 1.469 ns; Loc. = LAB_X72_Y41; Fanout = 3; COMB Node = 'c~496'
    Info: 4: + IC(0.210 ns) + CELL(0.381 ns) = 2.060 ns; Loc. = LAB_X72_Y41; Fanout = 11; COMB Node = 'Q~373'
    Info: 5: + IC(0.605 ns) + CELL(0.899 ns) = 3.564 ns; Loc. = LAB_X71_Y41; Fanout = 2; REG Node = 'j[6]'
    Info: Total cell delay = 1.480 ns ( 41.53 % )
    Info: Total interconnect delay = 2.084 ns ( 58.47 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X68_Y36 to location X79_Y47
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 258 megabytes of memory during processing
    Info: Processing ended: Mon Aug 20 13:05:09 2007
    Info: Elapsed time: 00:00:28