📄 m_generate.tan.rpt
字号:
; N/A ; 355.75 MHz ( period = 2.811 ns ) ; j[5] ; Q~reg0 ; clk ; clk ; None ; None ; 2.598 ns ;
; N/A ; 355.75 MHz ( period = 2.811 ns ) ; j[5] ; c[0] ; clk ; clk ; None ; None ; 2.598 ns ;
; N/A ; 359.32 MHz ( period = 2.783 ns ) ; j[5] ; c[4] ; clk ; clk ; None ; None ; 2.570 ns ;
; N/A ; 359.32 MHz ( period = 2.783 ns ) ; j[5] ; c[3] ; clk ; clk ; None ; None ; 2.570 ns ;
; N/A ; 359.32 MHz ( period = 2.783 ns ) ; j[5] ; c[2] ; clk ; clk ; None ; None ; 2.570 ns ;
; N/A ; 359.32 MHz ( period = 2.783 ns ) ; j[5] ; c[1] ; clk ; clk ; None ; None ; 2.570 ns ;
; N/A ; 366.70 MHz ( period = 2.727 ns ) ; p[3] ; c[4] ; clk ; clk ; None ; None ; 2.514 ns ;
; N/A ; 366.70 MHz ( period = 2.727 ns ) ; p[3] ; c[3] ; clk ; clk ; None ; None ; 2.514 ns ;
; N/A ; 366.70 MHz ( period = 2.727 ns ) ; p[3] ; c[2] ; clk ; clk ; None ; None ; 2.514 ns ;
; N/A ; 366.70 MHz ( period = 2.727 ns ) ; p[3] ; c[1] ; clk ; clk ; None ; None ; 2.514 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[0] ; c[0] ; clk ; clk ; None ; None ; 1.957 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[0] ; Q~reg0 ; clk ; clk ; None ; None ; 1.956 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[2] ; c[0] ; clk ; clk ; None ; None ; 1.894 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[2] ; Q~reg0 ; clk ; clk ; None ; None ; 1.893 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[1] ; c[0] ; clk ; clk ; None ; None ; 1.810 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[1] ; Q~reg0 ; clk ; clk ; None ; None ; 1.809 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[0] ; p[0] ; clk ; clk ; None ; None ; 1.803 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[0] ; p[3] ; clk ; clk ; None ; None ; 1.803 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; c[4] ; c[0] ; clk ; clk ; None ; None ; 1.786 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[3] ; p[2] ; clk ; clk ; None ; None ; 1.743 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; c[1] ; c[0] ; clk ; clk ; None ; None ; 1.633 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[3] ; c[0] ; clk ; clk ; None ; None ; 1.538 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[3] ; Q~reg0 ; clk ; clk ; None ; None ; 1.537 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[1] ; p[1] ; clk ; clk ; None ; None ; 1.502 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[1] ; p[0] ; clk ; clk ; None ; None ; 1.498 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[1] ; p[3] ; clk ; clk ; None ; None ; 1.497 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[0] ; p[1] ; clk ; clk ; None ; None ; 1.392 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[3] ; p[0] ; clk ; clk ; None ; None ; 1.347 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[3] ; p[3] ; clk ; clk ; None ; None ; 1.345 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[2] ; p[0] ; clk ; clk ; None ; None ; 1.258 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[2] ; p[3] ; clk ; clk ; None ; None ; 1.257 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; Q~reg0 ; Q~reg0 ; clk ; clk ; None ; None ; 1.174 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; c[0] ; c[0] ; clk ; clk ; None ; None ; 1.173 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[0] ; p[2] ; clk ; clk ; None ; None ; 1.126 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; c[4] ; Q~reg0 ; clk ; clk ; None ; None ; 1.119 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; c[1] ; c[2] ; clk ; clk ; None ; None ; 1.111 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[3] ; p[1] ; clk ; clk ; None ; None ; 1.062 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[2] ; p[2] ; clk ; clk ; None ; None ; 1.044 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; p[1] ; p[2] ; clk ; clk ; None ; None ; 0.965 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; c[0] ; c[1] ; clk ; clk ; None ; None ; 0.945 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; c[3] ; c[4] ; clk ; clk ; None ; None ; 0.771 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; c[2] ; c[3] ; clk ; clk ; None ; None ; 0.760 ns ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A ; None ; 7.752 ns ; Q~reg0 ; Q ; clk ;
+-------+--------------+------------+--------+----+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Mon Aug 20 13:05:35 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off M_generate -c M_generate --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 266.67 MHz between source register "j[1]" and destination register "j[6]" (period= 3.75 ns)
Info: + Longest register to register delay is 3.537 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X71_Y41_N2; Fanout = 4; REG Node = 'j[1]'
Info: 2: + IC(0.504 ns) + CELL(0.527 ns) = 1.031 ns; Loc. = LC_X71_Y41_N8; Fanout = 1; COMB Node = 'LessThan1~93'
Info: 3: + IC(0.645 ns) + CELL(0.100 ns) = 1.776 ns; Loc. = LC_X72_Y41_N1; Fanout = 3; COMB Node = 'c~496'
Info: 4: + IC(0.159 ns) + CELL(0.100 ns) = 2.035 ns; Loc. = LC_X72_Y41_N2; Fanout = 11; COMB Node = 'Q~373'
Info: 5: + IC(0.603 ns) + CELL(0.899 ns) = 3.537 ns; Loc. = LC_X71_Y41_N7; Fanout = 2; REG Node = 'j[6]'
Info: Total cell delay = 1.626 ns ( 45.97 % )
Info: Total interconnect delay = 1.911 ns ( 54.03 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 3.692 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_R3; Fanout = 17; CLK Node = 'clk'
Info: 2: + IC(2.049 ns) + CELL(0.644 ns) = 3.692 ns; Loc. = LC_X71_Y41_N7; Fanout = 2; REG Node = 'j[6]'
Info: Total cell delay = 1.643 ns ( 44.50 % )
Info: Total interconnect delay = 2.049 ns ( 55.50 % )
Info: - Longest clock path from clock "clk" to source register is 3.692 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_R3; Fanout = 17; CLK Node = 'clk'
Info: 2: + IC(2.049 ns) + CELL(0.644 ns) = 3.692 ns; Loc. = LC_X71_Y41_N2; Fanout = 4; REG Node = 'j[1]'
Info: Total cell delay = 1.643 ns ( 44.50 % )
Info: Total interconnect delay = 2.049 ns ( 55.50 % )
Info: + Micro clock to output delay of source is 0.202 ns
Info: + Micro setup delay of destination is 0.011 ns
Info: tco from clock "clk" to destination pin "Q" through register "Q~reg0" is 7.752 ns
Info: + Longest clock path from clock "clk" to source register is 3.692 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_R3; Fanout = 17; CLK Node = 'clk'
Info: 2: + IC(2.049 ns) + CELL(0.644 ns) = 3.692 ns; Loc. = LC_X73_Y41_N4; Fanout = 2; REG Node = 'Q~reg0'
Info: Total cell delay = 1.643 ns ( 44.50 % )
Info: Total interconnect delay = 2.049 ns ( 55.50 % )
Info: + Micro clock to output delay of source is 0.202 ns
Info: + Longest register to pin delay is 3.858 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X73_Y41_N4; Fanout = 2; REG Node = 'Q~reg0'
Info: 2: + IC(1.363 ns) + CELL(2.495 ns) = 3.858 ns; Loc. = PIN_H23; Fanout = 0; PIN Node = 'Q'
Info: Total cell delay = 2.495 ns ( 64.67 % )
Info: Total interconnect delay = 1.363 ns ( 35.33 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 103 megabytes of memory during processing
Info: Processing ended: Mon Aug 20 13:05:36 2007
Info: Elapsed time: 00:00:01
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