m_generate_vhd.sdo

m序列产生编码

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP1S25F672C7 Package FBGA672
// 

// 
// This SDF file should be used for ModelSim-Altera (VHDL) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "M_generate")
  (DATE "08/20/2007 13:05:43")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 6.1 Build 201 11/27/2006 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE clk_aI.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (999:999:999) (999:999:999))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE p_a1_a_aI.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (492:492:492) (500:500:500))
        (PORT datac (1084:1084:1084) (1073:1073:1073))
        (PORT datad (1122:1122:1122) (1076:1076:1076))
        (IOPATH datab regin (562:562:562) (562:562:562))
        (IOPATH datac regin (418:418:418) (418:418:418))
        (IOPATH datad regin (270:270:270) (270:270:270))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE p_a1_a_aI.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (768:768:768) (768:768:768))
        (PORT clk (2693:2693:2693) (2677:2677:2677))
        (IOPATH (posedge clk) regout (202:202:202) (202:202:202))
        (IOPATH (posedge aclr) regout (243:243:243) (243:243:243))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (11:11:11))
      (HOLD datain (posedge clk) (114:114:114))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE p_a3_a_aI.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1133:1133:1133) (1085:1085:1085))
        (PORT datab (695:695:695) (646:646:646))
        (PORT datac (1079:1079:1079) (1069:1069:1069))
        (PORT datad (1075:1075:1075) (1048:1048:1048))
        (IOPATH dataa regin (670:670:670) (670:670:670))
        (IOPATH datab regin (562:562:562) (562:562:562))
        (IOPATH datac regin (418:418:418) (418:418:418))
        (IOPATH datad regin (270:270:270) (270:270:270))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE p_a3_a_aI.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (768:768:768) (768:768:768))
        (PORT clk (2693:2693:2693) (2677:2677:2677))
        (IOPATH (posedge clk) regout (202:202:202) (202:202:202))
        (IOPATH (posedge aclr) regout (243:243:243) (243:243:243))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (11:11:11))
      (HOLD datain (posedge clk) (114:114:114))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE p_a2_a_aI.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1073:1073:1073) (1057:1057:1057))
        (PORT datab (468:468:468) (482:482:482))
        (PORT datac (708:708:708) (672:672:672))
        (PORT datad (695:695:695) (648:648:648))
        (IOPATH dataa regin (670:670:670) (670:670:670))
        (IOPATH datab regin (562:562:562) (562:562:562))
        (IOPATH datac regin (418:418:418) (418:418:418))
        (IOPATH datad regin (270:270:270) (270:270:270))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE p_a2_a_aI.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (768:768:768) (768:768:768))
        (PORT clk (2693:2693:2693) (2677:2677:2677))
        (IOPATH (posedge clk) regout (202:202:202) (202:202:202))
        (IOPATH (posedge aclr) regout (243:243:243) (243:243:243))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (11:11:11))
      (HOLD datain (posedge clk) (114:114:114))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE p_a0_a_aI.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1133:1133:1133) (1087:1087:1087))
        (PORT datab (696:696:696) (649:649:649))
        (PORT datac (1080:1080:1080) (1070:1070:1070))
        (PORT datad (1077:1077:1077) (1050:1050:1050))
        (IOPATH dataa regin (670:670:670) (670:670:670))
        (IOPATH datab regin (562:562:562) (562:562:562))
        (IOPATH datac regin (418:418:418) (418:418:418))
        (IOPATH datad regin (270:270:270) (270:270:270))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE p_a0_a_aI.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (768:768:768) (768:768:768))
        (PORT clk (2693:2693:2693) (2677:2677:2677))
        (IOPATH (posedge clk) regout (202:202:202) (202:202:202))
        (IOPATH (posedge aclr) regout (243:243:243) (243:243:243))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (11:11:11))
      (HOLD datain (posedge clk) (114:114:114))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE LessThan0_a52_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (486:486:486) (494:494:494))
        (PORT datab (483:483:483) (493:493:493))
        (PORT datac (714:714:714) (680:680:680))
        (PORT datad (500:500:500) (502:502:502))
        (IOPATH dataa combout (527:527:527) (527:527:527))
        (IOPATH datab combout (381:381:381) (381:381:381))
        (IOPATH datac combout (244:244:244) (244:244:244))
        (IOPATH datad combout (100:100:100) (100:100:100))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE Q_a373_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (394:394:394) (420:420:420))
        (PORT datad (159:159:159) (159:159:159))
        (IOPATH datac combout (244:244:244) (244:244:244))
        (IOPATH datad combout (100:100:100) (100:100:100))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE j_a0_a_aI.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (689:689:689) (643:643:643))
        (IOPATH dataa regin (670:670:670) (670:670:670))
        (IOPATH dataa cout0 (509:509:509) (509:509:509))
        (IOPATH dataa cout1 (518:518:518) (518:518:518))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE j_a0_a_aI.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1502:1502:1502) (1487:1487:1487))
        (PORT aclr (768:768:768) (768:768:768))
        (PORT clk (2693:2693:2693) (2677:2677:2677))
        (IOPATH (posedge clk) regout (202:202:202) (202:202:202))
        (IOPATH (posedge aclr) regout (243:243:243) (243:243:243))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (11:11:11))
      (SETUP sclr (posedge clk) (11:11:11))
      (HOLD datain (posedge clk) (114:114:114))
      (HOLD sclr (posedge clk) (114:114:114))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE j_a1_a_aI.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (665:665:665) (624:624:624))
        (IOPATH datab regin (562:562:562) (562:562:562))
        (IOPATH cin0 regin (656:656:656) (656:656:656))
        (IOPATH cin1 regin (675:675:675) (675:675:675))
        (IOPATH datab cout0 (395:395:395) (395:395:395))
        (IOPATH cin0 cout0 (69:69:69) (69:69:69))
        (IOPATH datab cout1 (392:392:392) (392:392:392))
        (IOPATH cin1 cout1 (71:71:71) (71:71:71))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE j_a1_a_aI.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1502:1502:1502) (1487:1487:1487))
        (PORT aclr (768:768:768) (768:768:768))
        (PORT clk (2693:2693:2693) (2677:2677:2677))
        (IOPATH (posedge clk) regout (202:202:202) (202:202:202))
        (IOPATH (posedge aclr) regout (243:243:243) (243:243:243))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (11:11:11))
      (SETUP sclr (posedge clk) (11:11:11))
      (HOLD datain (posedge clk) (114:114:114))
      (HOLD sclr (posedge clk) (114:114:114))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE j_a2_a_aI.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (686:686:686) (641:641:641))
        (IOPATH dataa regin (670:670:670) (670:670:670))
        (IOPATH cin0 regin (656:656:656) (656:656:656))
        (IOPATH cin1 regin (675:675:675) (675:675:675))
        (IOPATH dataa cout0 (509:509:509) (509:509:509))
        (IOPATH cin0 cout0 (69:69:69) (69:69:69))
        (IOPATH dataa cout1 (518:518:518) (518:518:518))
        (IOPATH cin1 cout1 (71:71:71) (71:71:71))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE j_a2_a_aI.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1502:1502:1502) (1487:1487:1487))
        (PORT aclr (768:768:768) (768:768:768))
        (PORT clk (2693:2693:2693) (2677:2677:2677))
        (IOPATH (posedge clk) regout (202:202:202) (202:202:202))
        (IOPATH (posedge aclr) regout (243:243:243) (243:243:243))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (11:11:11))
      (SETUP sclr (posedge clk) (11:11:11))
      (HOLD datain (posedge clk) (114:114:114))
      (HOLD sclr (posedge clk) (114:114:114))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE j_a3_a_aI.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (661:661:661) (621:621:621))
        (IOPATH datab regin (562:562:562) (562:562:562))
        (IOPATH cin0 regin (656:656:656) (656:656:656))
        (IOPATH cin1 regin (675:675:675) (675:675:675))
        (IOPATH datab cout (529:529:529) (529:529:529))
        (IOPATH cin0 cout (155:155:155) (155:155:155))
        (IOPATH cin1 cout (141:141:141) (141:141:141))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE j_a3_a_aI.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1502:1502:1502) (1487:1487:1487))
        (PORT aclr (768:768:768) (768:768:768))
        (PORT clk (2693:2693:2693) (2677:2677:2677))
        (IOPATH (posedge clk) regout (202:202:202) (202:202:202))
        (IOPATH (posedge aclr) regout (243:243:243) (243:243:243))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (11:11:11))
      (SETUP sclr (posedge clk) (11:11:11))
      (HOLD datain (posedge clk) (114:114:114))
      (HOLD sclr (posedge clk) (114:114:114))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE j_a4_a_aI.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (471:471:471) (480:480:480))
        (IOPATH datab regin (562:562:562) (562:562:562))