m_generate.vho

m序列产生编码

	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datab => j(3),
	aclr => GND,
	sclr => Q_a373,
	cin0 => j_a2_a_a92,
	cin1 => j_a2_a_a92COUT1_105,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => j(3),
	cout => j_a3_a_a93);

j_a4_a_aI : stratix_lcell
-- Equation(s):
-- j(4) = DFFEAS(j(4) $ !j_a3_a_a93, GLOBAL(clk_acombout), VCC, , , , , Q_a373, )
-- j_a4_a_a89 = CARRY(j(4) & !j_a3_a_a93)
-- j_a4_a_a89COUT1_107 = CARRY(j(4) & !j_a3_a_a93)

-- pragma translate_off
GENERIC MAP (
	cin_used => "true",
	lut_mask => "c30c",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datab => j(4),
	aclr => GND,
	sclr => Q_a373,
	cin => j_a3_a_a93,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => j(4),
	cout0 => j_a4_a_a89,
	cout1 => j_a4_a_a89COUT1_107);

j_a5_a_aI : stratix_lcell
-- Equation(s):
-- j(5) = DFFEAS(j(5) $ (!j_a3_a_a93 & j_a4_a_a89) # (j_a3_a_a93 & j_a4_a_a89COUT1_107), GLOBAL(clk_acombout), VCC, , , , , Q_a373, )
-- j_a5_a_a88 = CARRY(!j_a4_a_a89 # !j(5))
-- j_a5_a_a88COUT1_109 = CARRY(!j_a4_a_a89COUT1_107 # !j(5))

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	cin_used => "true",
	lut_mask => "3c3f",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datab => j(5),
	aclr => GND,
	sclr => Q_a373,
	cin => j_a3_a_a93,
	cin0 => j_a4_a_a89,
	cin1 => j_a4_a_a89COUT1_107,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => j(5),
	cout0 => j_a5_a_a88,
	cout1 => j_a5_a_a88COUT1_109);

j_a6_a_aI : stratix_lcell
-- Equation(s):
-- j(6) = DFFEAS(j(6) $ (!(!j_a3_a_a93 & j_a5_a_a88) # (j_a3_a_a93 & j_a5_a_a88COUT1_109)), GLOBAL(clk_acombout), VCC, , , , , Q_a373, )

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	cin_used => "true",
	lut_mask => "a5a5",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => j(6),
	aclr => GND,
	sclr => Q_a373,
	cin => j_a3_a_a93,
	cin0 => j_a5_a_a88,
	cin1 => j_a5_a_a88COUT1_109,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => j(6));

LessThan1_a93_I : stratix_lcell
-- Equation(s):
-- LessThan1_a93 = !j(2) & !j(3) & (!j(0) # !j(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0007",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => j(1),
	datab => j(0),
	datac => j(2),
	datad => j(3),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => LessThan1_a93);

c_a496_I : stratix_lcell
-- Equation(s):
-- c_a496 = j(6) & j(5) & (j(4) # !LessThan1_a93)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "8088",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => j(6),
	datab => j(5),
	datac => j(4),
	datad => LessThan1_a93,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => c_a496);

c_a0_I : stratix_lcell
-- Equation(s):
-- c_a0 = c(4) $ c(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0ff0",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datac => c(4),
	datad => c(1),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => c_a0);

c_a0_a_aI : stratix_lcell
-- Equation(s):
-- c(0) = DFFEAS(LessThan0_a52 # c_a496 & (c_a0) # !c_a496 & c(0), GLOBAL(clk_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "ffe2",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => c(0),
	datab => c_a496,
	datac => c_a0,
	datad => LessThan0_a52,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => c(0));

c_a1_a_aI : stratix_lcell
-- Equation(s):
-- c(1) = DFFEAS(!LessThan0_a52 & (c(0)), GLOBAL(clk_acombout), VCC, , Q_a373, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "5500",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => LessThan0_a52,
	datad => c(0),
	aclr => GND,
	ena => Q_a373,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => c(1));

c_a2_a_aI : stratix_lcell
-- Equation(s):
-- c(2) = DFFEAS(c(1) & !LessThan0_a52, GLOBAL(clk_acombout), VCC, , Q_a373, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "00f0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datac => c(1),
	datad => LessThan0_a52,
	aclr => GND,
	ena => Q_a373,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => c(2));

c_a3_a_aI : stratix_lcell
-- Equation(s):
-- c(3) = DFFEAS(!LessThan0_a52 & (c(2)), GLOBAL(clk_acombout), VCC, , Q_a373, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "5500",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => LessThan0_a52,
	datad => c(2),
	aclr => GND,
	ena => Q_a373,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => c(3));

c_a4_a_aI : stratix_lcell
-- Equation(s):
-- c(4) = DFFEAS(!LessThan0_a52 & (c(3)), GLOBAL(clk_acombout), VCC, , Q_a373, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "5500",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => LessThan0_a52,
	datad => c(3),
	aclr => GND,
	ena => Q_a373,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => c(4));

Q_areg0_I : stratix_lcell
-- Equation(s):
-- Q_areg0 = DFFEAS(c_a496 & (c(4)) # !c_a496 & (LessThan0_a52 & (c(4)) # !LessThan0_a52 & Q_areg0), GLOBAL(clk_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "f0e2",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => Q_areg0,
	datab => c_a496,
	datac => c(4),
	datad => LessThan0_a52,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => Q_areg0);

Q_aI : stratix_io
-- pragma translate_off
GENERIC MAP (
	ddio_mode => "none",
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => Q_areg0,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_Q);
END structure;