m_generate.vho

m序列产生编码

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.1 Build 201 11/27/2006 SJ Full Version"

-- DATE "08/20/2007 13:05:43"

-- 
-- Device: Altera EP1S25F672C7 Package FBGA672
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY IEEE, stratix;
USE IEEE.std_logic_1164.all;
USE stratix.stratix_components.all;

ENTITY 	M_generate IS
    PORT (
	clk : IN std_logic;
	Q : OUT std_logic
	);
END M_generate;

ARCHITECTURE structure OF M_generate IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_Q : std_logic;
SIGNAL clk_acombout : std_logic;
SIGNAL LessThan0_a52 : std_logic;
SIGNAL Q_a373 : std_logic;
SIGNAL j_a0_a_a90 : std_logic;
SIGNAL j_a0_a_a90COUT1_101 : std_logic;
SIGNAL j_a1_a_a91 : std_logic;
SIGNAL j_a1_a_a91COUT1_103 : std_logic;
SIGNAL j_a2_a_a92 : std_logic;
SIGNAL j_a2_a_a92COUT1_105 : std_logic;
SIGNAL j_a3_a_a93 : std_logic;
SIGNAL j_a4_a_a89 : std_logic;
SIGNAL j_a4_a_a89COUT1_107 : std_logic;
SIGNAL j_a5_a_a88 : std_logic;
SIGNAL j_a5_a_a88COUT1_109 : std_logic;
SIGNAL LessThan1_a93 : std_logic;
SIGNAL c_a496 : std_logic;
SIGNAL c_a0 : std_logic;
SIGNAL Q_areg0 : std_logic;
SIGNAL c : std_logic_vector(4 DOWNTO 0);
SIGNAL j : std_logic_vector(6 DOWNTO 0);
SIGNAL p : std_logic_vector(3 DOWNTO 0);

BEGIN

ww_clk <= clk;
Q <= ww_Q;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

clk_aI : stratix_io
-- pragma translate_off
GENERIC MAP (
	ddio_mode => "none",
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => clk_acombout);

p_a1_a_aI : stratix_lcell
-- Equation(s):
-- p(1) = DFFEAS(p(1) $ (!p(3) & p(0)), GLOBAL(clk_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "c3f0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datab => p(3),
	datac => p(1),
	datad => p(0),
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => p(1));

p_a3_a_aI : stratix_lcell
-- Equation(s):
-- p(3) = DFFEAS(p(3) # p(0) & p(2) & p(1), GLOBAL(clk_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "ff80",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => p(0),
	datab => p(2),
	datac => p(1),
	datad => p(3),
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => p(3));

p_a2_a_aI : stratix_lcell
-- Equation(s):
-- p(2) = DFFEAS(p(2) $ (!p(3) & p(0) & p(1)), GLOBAL(clk_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "9ccc",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => p(3),
	datab => p(2),
	datac => p(0),
	datad => p(1),
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => p(2));

p_a0_a_aI : stratix_lcell
-- Equation(s):
-- p(0) = DFFEAS(p(0) & (p(3)) # !p(0) & (!p(2) & !p(1) # !p(3)), GLOBAL(clk_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "ab55",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => p(0),
	datab => p(2),
	datac => p(1),
	datad => p(3),
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => p(0));

LessThan0_a52_I : stratix_lcell
-- Equation(s):
-- LessThan0_a52 = !p(0) & !p(1) & !p(2) # !p(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "01ff",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => p(0),
	datab => p(1),
	datac => p(2),
	datad => p(3),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => LessThan0_a52);

Q_a373_I : stratix_lcell
-- Equation(s):
-- Q_a373 = LessThan0_a52 # c_a496

-- pragma translate_off
GENERIC MAP (
	lut_mask => "fff0",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datac => LessThan0_a52,
	datad => c_a496,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Q_a373);

j_a0_a_aI : stratix_lcell
-- Equation(s):
-- j(0) = DFFEAS(!j(0), GLOBAL(clk_acombout), VCC, , , , , Q_a373, )
-- j_a0_a_a90 = CARRY(j(0))
-- j_a0_a_a90COUT1_101 = CARRY(j(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "55aa",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => j(0),
	aclr => GND,
	sclr => Q_a373,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => j(0),
	cout0 => j_a0_a_a90,
	cout1 => j_a0_a_a90COUT1_101);

j_a1_a_aI : stratix_lcell
-- Equation(s):
-- j(1) = DFFEAS(j(1) $ j_a0_a_a90, GLOBAL(clk_acombout), VCC, , , , , Q_a373, )
-- j_a1_a_a91 = CARRY(!j_a0_a_a90 # !j(1))
-- j_a1_a_a91COUT1_103 = CARRY(!j_a0_a_a90COUT1_101 # !j(1))

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	lut_mask => "3c3f",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datab => j(1),
	aclr => GND,
	sclr => Q_a373,
	cin0 => j_a0_a_a90,
	cin1 => j_a0_a_a90COUT1_101,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => j(1),
	cout0 => j_a1_a_a91,
	cout1 => j_a1_a_a91COUT1_103);

j_a2_a_aI : stratix_lcell
-- Equation(s):
-- j(2) = DFFEAS(j(2) $ (!j_a1_a_a91), GLOBAL(clk_acombout), VCC, , , , , Q_a373, )
-- j_a2_a_a92 = CARRY(j(2) & (!j_a1_a_a91))
-- j_a2_a_a92COUT1_105 = CARRY(j(2) & (!j_a1_a_a91COUT1_103))

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	lut_mask => "a50a",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => j(2),
	aclr => GND,
	sclr => Q_a373,
	cin0 => j_a1_a_a91,
	cin1 => j_a1_a_a91COUT1_103,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => j(2),
	cout0 => j_a2_a_a92,
	cout1 => j_a2_a_a92COUT1_105);

j_a3_a_aI : stratix_lcell
-- Equation(s):
-- j(3) = DFFEAS(j(3) $ j_a2_a_a92, GLOBAL(clk_acombout), VCC, , , , , Q_a373, )
-- j_a3_a_a93 = CARRY(!j_a2_a_a92COUT1_105 # !j(3))

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	lut_mask => "3c3f",