pie_code.fit.smsg

pie edcode编码 程序设计

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 11 09:58:47 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off pie_code -c pie_code
Info: Selected device EP2C35F672C7 for design "pie_code"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 638 of 638 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C50F672C7 is compatible
    Info: Device EP2C70F672C7 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location E3
    Info: Pin ~nCSO~ is reserved at location D3
    Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: No exact pin location assignment(s) for 23 pins of 23 total pins
    Info: Pin data_ready not assigned to an exact location on the device
    Info: Pin data_valid not assigned to an exact location on the device
    Info: Pin data_out[16] not assigned to an exact location on the device
    Info: Pin data_out[15] not assigned to an exact location on the device
    Info: Pin data_out[14] not assigned to an exact location on the device
    Info: Pin data_out[13] not assigned to an exact location on the device
    Info: Pin data_out[12] not assigned to an exact location on the device
    Info: Pin data_out[11] not assigned to an exact location on the device
    Info: Pin data_out[10] not assigned to an exact location on the device
    Info: Pin data_out[9] not assigned to an exact location on the device
    Info: Pin data_out[8] not assigned to an exact location on the device
    Info: Pin data_out[7] not assigned to an exact location on the device
    Info: Pin data_out[6] not assigned to an exact location on the device
    Info: Pin data_out[5] not assigned to an exact location on the device
    Info: Pin data_out[4] not assigned to an exact location on the device
    Info: Pin data_out[3] not assigned to an exact location on the device
    Info: Pin data_out[2] not assigned to an exact location on the device
    Info: Pin data_out[1] not assigned to an exact location on the device
    Info: Pin data_out[0] not assigned to an exact location on the device
    Info: Pin source_error[1] not assigned to an exact location on the device
    Info: Pin source_error[0] not assigned to an exact location on the device
    Info: Pin clock not assigned to an exact location on the device
    Info: Pin data_in not assigned to an exact location on the device
Info: Automatically promoted node clock (placed in PIN P2 (CLK2, LVDSCLK1p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 22 (unused VREF, 3.30 VCCIO, 1 input, 21 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  63 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  57 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  56 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  58 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  65 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  58 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  58 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  56 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to memory delay of 4.230 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X28_Y24; Fanout = 13; REG Node = 'fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff'
    Info: 2: + IC(2.019 ns) + CELL(0.178 ns) = 2.197 ns; Loc. = LAB_X38_Y20; Fanout = 2; COMB Node = 'fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|ram_read_address[1]~40'
    Info: 3: + IC(1.874 ns) + CELL(0.159 ns) = 4.230 ns; Loc. = M4K_X26_Y24; Fanout = 1; MEM Node = 'fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg1'
    Info: Total cell delay = 0.337 ns ( 7.97 % )
    Info: Total interconnect delay = 3.893 ns ( 92.03 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location X33_Y12 to location X43_Y23
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 21 output pins without output pin load capacitance assignment
    Info: Pin "data_ready" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_valid" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "source_error[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "source_error[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin source_error[1] has GND driving its datain port
    Info: Pin source_error[0] has GND driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 4 warnings
    Info: Allocated 225 megabytes of memory during processing
    Info: Processing ended: Tue Sep 11 09:59:07 2007
    Info: Elapsed time: 00:00:20