pie_code.hif

pie edcode编码 程序设计

AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|rom_lut_r_cen.v
bd2d9246d887c02de8932667ab03f
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
C0
0
PARAMETER_SIGNED_DEC
USR
C1
70
PARAMETER_SIGNED_DEC
USR
C2
854
PARAMETER_SIGNED_DEC
USR
C3
924
PARAMETER_SIGNED_DEC
USR
C4
834
PARAMETER_SIGNED_DEC
USR
C5
904
PARAMETER_SIGNED_DEC
USR
C6
664
PARAMETER_SIGNED_DEC
USR
C7
734
PARAMETER_SIGNED_DEC
USR
C8
380
PARAMETER_SIGNED_DEC
USR
C9
450
PARAMETER_SIGNED_DEC
USR
CA
210
PARAMETER_SIGNED_DEC
USR
CB
280
PARAMETER_SIGNED_DEC
USR
CC
190
PARAMETER_SIGNED_DEC
USR
CD
260
PARAMETER_SIGNED_DEC
USR
CE
20
PARAMETER_SIGNED_DEC
USR
CF
90
PARAMETER_SIGNED_DEC
USR
DATA_WIDTH
10
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur3_n_0_pp
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur3_n_1_pp
}
# end
# entity
rom_lut_r_cen
# storage
db|pie_code.(20).cnf
db|pie_code.(20).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|rom_lut_r_cen.v
bd2d9246d887c02de8932667ab03f
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
C0
0
PARAMETER_SIGNED_DEC
USR
C1
1881
PARAMETER_SIGNED_DEC
USR
C2
4192
PARAMETER_SIGNED_DEC
USR
C3
6073
PARAMETER_SIGNED_DEC
USR
C4
6622
PARAMETER_SIGNED_DEC
USR
C5
8503
PARAMETER_SIGNED_DEC
USR
C6
10814
PARAMETER_SIGNED_DEC
USR
C7
12695
PARAMETER_SIGNED_DEC
USR
C8
8191
PARAMETER_SIGNED_DEC
USR
C9
10072
PARAMETER_SIGNED_DEC
USR
CA
12383
PARAMETER_SIGNED_DEC
USR
CB
14264
PARAMETER_SIGNED_DEC
USR
CC
14813
PARAMETER_SIGNED_DEC
USR
CD
16694
PARAMETER_SIGNED_DEC
USR
CE
19005
PARAMETER_SIGNED_DEC
USR
CF
20886
PARAMETER_SIGNED_DEC
USR
DATA_WIDTH
16
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur4_n_0_pp
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur4_n_1_pp
}
# end
# entity
sadd_lpm_cen
# storage
db|pie_code.(21).cnf
db|pie_code.(21).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|sadd_lpm_cen.v
62aa4e6e1b65434bef7a771f690f887
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IN_WIDTH
17
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_0_n
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_3_lut_l_0_n_0_n
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_4_lut_l_0_n_0_n
}
# end
# entity
sadd_lpm_cen
# storage
db|pie_code.(22).cnf
db|pie_code.(22).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|sadd_lpm_cen.v
62aa4e6e1b65434bef7a771f690f887
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IN_WIDTH
18
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_0_n_0_n
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_0_n_1_n
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_0_n_2_n
}
# end
# entity
sadd_lpm_cen
# storage
db|pie_code.(23).cnf
db|pie_code.(23).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|sadd_lpm_cen.v
62aa4e6e1b65434bef7a771f690f887
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IN_WIDTH
19
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_1_n
}
# end
# entity
sadd_lpm_cen
# storage
db|pie_code.(24).cnf
db|pie_code.(24).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|sadd_lpm_cen.v
62aa4e6e1b65434bef7a771f690f887
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IN_WIDTH
20
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n
}
# end
# entity
mac_tl
# storage
db|pie_code.(25).cnf
db|pie_code.(25).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|mac_tl.v
f8dfa8ea226692edae9632f969a49b8
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
DATA_WIDTH
21
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|mac_tl:Umtl
}
# end
# entity
par_ctrl
# storage
db|pie_code.(26).cnf
db|pie_code.(26).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|par_ctrl.v
878dfc0242d30e9bee11a611db8a3b7
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
REG_LEN
7
PARAMETER_SIGNED_DEC
USR
REG_BIT
3
PARAMETER_SIGNED_DEC
USR
CH_WIDTH
0
PARAMETER_SIGNED_DEC
USR
NUM_CH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|par_ctrl:Uctrl
}
# end
# entity
auk_dspip_avalon_streaming_sink
# storage
db|pie_code.(13).cnf
db|pie_code.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
auk_dspip_avalon_streaming_sink.vhd
fda3bacc6665638eead6e3a32796ce1
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
width_g
4
PARAMETER_SIGNED_DEC
USR
packet_size_g
1
PARAMETER_SIGNED_DEC
USR
fifo_depth_g
5
PARAMETER_SIGNED_DEC
USR
min_data_count_g
2
PARAMETER_SIGNED_DEC
USR
pfc_mode_g
false
PARAMETER_ENUM
USR
sop_eop_calc_g
false
PARAMETER_ENUM
USR
family_g
Cyclone II
PARAMETER_STRING
USR
mem_type_g
Auto
PARAMETER_STRING
USR
 constraint(data)
3 downto 0
PARAMETER_STRING
USR
 constraint(packet_error)
1 downto 0
PARAMETER_STRING
USR
 constraint(at_sink_data)
3 downto 0
PARAMETER_STRING
USR
 constraint(at_sink_error)
1 downto 0
PARAMETER_STRING
USR
}
# include_file {
auk_dspip_math_pkg.vhd
25746ad2295926525aa5743d99f3d3d
auk_dspip_lib_pkg.vhd
1434b72bd12b55dbe7d63e12f6e7d
}
# end
# entity
scfifo
# storage
db|pie_code.(27).cnf
db|pie_code.(27).cnf
# case_insensitive
# source_file
..|..|..|quartus|libraries|megafunctions|scfifo.tdf
35622eb715ad7962dc948ede2925d2b
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
6
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
5
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
3
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
ON
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
3
PARAMETER_SIGNED_DEC
USR
ALMOST_EMPTY_VALUE
1
PARAMETER_SIGNED_DEC
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_ged1
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw0
-1
3
sclr
-1
3
rdreq
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
empty
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# include_file {
..|..|..|quartus|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
..|..|..|quartus|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
..|..|..|quartus|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
..|..|..|quartus|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
..|..|..|quartus|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
..|..|..|quartus|libraries|megafunctions|aglobal61.inc
b513fb574ceb8f5886cd4ba429e82ec
}
# end
# entity
scfifo_ged1
# storage
db|pie_code.(28).cnf
db|pie_code.(28).cnf
# case_insensitive
# source_file
db|scfifo_ged1.tdf
b3e716b94f136e6bd28f7b1f7e52298d
6
# used_port {
wrreq
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rdreq
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
empty
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# end
# entity
a_dpfifo_l551
# storage
db|pie_code.(29).cnf
db|pie_code.(29).cnf
# case_insensitive
# source_file
db|a_dpfifo_l551.tdf
443ec382353e8fd655a94755b8fd11fb
6
# used_port {
wreq
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
empty
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# end
# entity
altsyncram_8lf1
# storage
db|pie_code.(30).cnf
db|pie_code.(30).cnf
# case_insensitive
# source_file
db|altsyncram_8lf1.tdf
6b98a155bb7d4964217cdcb6a85648e
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# end
# entity
auk_dspip_avalon_streaming_source
# storage
db|pie_code.(31).cnf
db|pie_code.(31).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
auk_dspip_avalon_streaming_source.vhd
a21f158f6c9ae54d6afa6f9d1adb577
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
width_g
18
PARAMETER_SIGNED_DEC
USR
packet_size_g
1
PARAMETER_SIGNED_DEC
USR
have_counter_g
false
PARAMETER_ENUM
USR
counter_limit_g
4
PARAMETER_SIGNED_DEC
USR
multi_channel_g
true
PARAMETER_ENUM
USR
 constraint(data)
17 downto 0
PARAMETER_STRING
USR
 constraint(data_count)
0 downto 0
PARAMETER_STRING
USR
 constraint(packet_error)
1 downto 0
PARAMETER_STRING
USR
 constraint(at_source_data)
17 downto 0
PARAMETER_STRING
USR
 constraint(at_source_channel)
0 downto 0
PARAMETER_STRING
USR
 constraint(at_source_error)
1 downto 0
PARAMETER_STRING
USR
}
# include_file {
auk_dspip_math_pkg.vhd
25746ad2295926525aa5743d99f3d3d
}
# end
# entity
delay_trig_cen
# storage
db|pie_code.(34).cnf
db|pie_code.(34).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|delay_trig_cen.v
b9a949c0a531793446d8de2fdb5de59
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IN_WIDTH
3
PARAMETER_SIGNED_DEC
USR
WHOLE_DELAY
1
PARAMETER_SIGNED_DEC
USR
FINE_DELAY
8
PARAMETER_SIGNED_DEC
USR
}
# end
# entity
tdl_da_lc
# storage
db|pie_code.(35).cnf
db|pie_code.(35).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|tdl_da_lc.v
308971e2fd5045b5e49bdf3185df66a
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
WIDTH
4
PARAMETER_SIGNED_DEC
USR
}
# end
# entity
rom_mset_lut_r_cen
# storage
db|pie_code.(36).cnf
db|pie_code.(36).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|rom_mset_lut_r_cen.v
ba6b3fadab95763987a45a64364c9ee
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
C_1_0
0
PARAMETER_SIGNED_DEC
USR
C_1_1
3
PARAMETER_SIGNED_DEC
USR
C_1_2
32761
PARAMETER_SIGNED_DEC
USR
C_1_3
32764
PARAMETER_SIGNED_DEC
USR
C_1_4
0
PARAMETER_SIGNED_DEC
USR
C_1_5
3
PARAMETER_SIGNED_DEC
USR
C_1_6
32761
PARAMETER_SIGNED_DEC
USR
C_1_7
32764
PARAMETER_SIGNED_DEC
USR
C_1_8
8191
PARAMETER_SIGNED_DEC
USR
C_1_9
8194
PARAMETER_SIGNED_DEC
USR
C_1_A
8184
PARAMETER_SIGNED_DEC