pie_code.tan.qmsg

pie edcode编码 程序设计

{ "Info" "ITDB_FULL_TCO_RESULT" "clock data_out\[0\] fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_source:source\|at_source_data\[0\] 8.778 ns register " "Info: tco from clock \"clock\" to destination pin \"data_out\[0\]\" through register \"fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_source:source\|at_source_data\[0\]\" is 8.778 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.923 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 216 -40 128 232 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.179 ns) + CELL(0.000 ns) 1.215 ns clock~clkctrl 2 COMB CLKCTRL_G3 375 " "Info: 2: + IC(0.179 ns) + CELL(0.000 ns) = 1.215 ns; Loc. = CLKCTRL_G3; Fanout = 375; COMB Node = 'clock~clkctrl'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.179 ns" { clock clock~clkctrl } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 216 -40 128 232 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.106 ns) + CELL(0.602 ns) 2.923 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_source:source\|at_source_data\[0\] 3 REG LCFF_X40_Y19_N27 1 " "Info: 3: + IC(1.106 ns) + CELL(0.602 ns) = 2.923 ns; Loc. = LCFF_X40_Y19_N27; Fanout = 1; REG Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_source:source\|at_source_data\[0\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.708 ns" { clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|at_source_data[0] } "NODE_NAME" } } { "auk_dspip_avalon_streaming_source.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_source.vhd" 350 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.638 ns ( 56.04 % ) " "Info: Total cell delay = 1.638 ns ( 56.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.285 ns ( 43.96 % ) " "Info: Total interconnect delay = 1.285 ns ( 43.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.923 ns" { clock clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|at_source_data[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.923 ns" { clock clock~combout clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|at_source_data[0] } { 0.000ns 0.000ns 0.179ns 1.106ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "auk_dspip_avalon_streaming_source.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_source.vhd" 350 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.578 ns + Longest register pin " "Info: + Longest register to pin delay is 5.578 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_source:source\|at_source_data\[0\] 1 REG LCFF_X40_Y19_N27 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y19_N27; Fanout = 1; REG Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_source:source\|at_source_data\[0\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|at_source_data[0] } "NODE_NAME" } } { "auk_dspip_avalon_streaming_source.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_source.vhd" 350 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.592 ns) + CELL(2.986 ns) 5.578 ns data_out\[0\] 2 PIN PIN_Y15 0 " "Info: 2: + IC(2.592 ns) + CELL(2.986 ns) = 5.578 ns; Loc. = PIN_Y15; Fanout = 0; PIN Node = 'data_out\[0\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.578 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|at_source_data[0] data_out[0] } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 216 448 624 232 "data_out\[16..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.986 ns ( 53.53 % ) " "Info: Total cell delay = 2.986 ns ( 53.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.592 ns ( 46.47 % ) " "Info: Total interconnect delay = 2.592 ns ( 46.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.578 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|at_source_data[0] data_out[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "5.578 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|at_source_data[0] data_out[0] } { 0.000ns 2.592ns } { 0.000ns 2.986ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.923 ns" { clock clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|at_source_data[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.923 ns" { clock clock~combout clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|at_source_data[0] } { 0.000ns 0.000ns 0.179ns 1.106ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.578 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|at_source_data[0] data_out[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "5.578 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|at_source_data[0] data_out[0] } { 0.000ns 2.592ns } { 0.000ns 2.986ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\] data_in clock 0.340 ns register " "Info: th for register \"fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\]\" (data pin = \"data_in\", clock pin = \"clock\") is 0.340 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.921 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 216 -40 128 232 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.179 ns) + CELL(0.000 ns) 1.215 ns clock~clkctrl 2 COMB CLKCTRL_G3 375 " "Info: 2: + IC(0.179 ns) + CELL(0.000 ns) = 1.215 ns; Loc. = CLKCTRL_G3; Fanout = 375; COMB Node = 'clock~clkctrl'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.179 ns" { clock clock~clkctrl } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 216 -40 128 232 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.104 ns) + CELL(0.602 ns) 2.921 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\] 3 REG LCFF_X28_Y24_N1 2 " "Info: 3: + IC(1.104 ns) + CELL(0.602 ns) = 2.921 ns; Loc. = LCFF_X28_Y24_N1; Fanout = 2; REG Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.706 ns" { clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } "NODE_NAME" } } { "auk_dspip_avalon_streaming_sink.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_sink.vhd" 473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.638 ns ( 56.08 % ) " "Info: Total cell delay = 1.638 ns ( 56.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.283 ns ( 43.92 % ) " "Info: Total interconnect delay = 1.283 ns ( 43.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { clock clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { clock clock~combout clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } { 0.000ns 0.000ns 0.179ns 1.104ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "auk_dspip_avalon_streaming_sink.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_sink.vhd" 473 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.867 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.016 ns) 1.016 ns data_in 1 PIN PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(1.016 ns) = 1.016 ns; Loc. = PIN_C13; Fanout = 1; PIN Node = 'data_in'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 248 -40 128 264 "data_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.577 ns) + CELL(0.178 ns) 2.771 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\]~52 2 COMB LCCOMB_X28_Y24_N0 1 " "Info: 2: + IC(1.577 ns) + CELL(0.178 ns) = 2.771 ns; Loc. = LCCOMB_X28_Y24_N0; Fanout = 1; COMB Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\]~52'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.755 ns" { data_in fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]~52 } "NODE_NAME" } } { "auk_dspip_avalon_streaming_sink.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_sink.vhd" 473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.867 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\] 3 REG LCFF_X28_Y24_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 2.867 ns; Loc. = LCFF_X28_Y24_N1; Fanout = 2; REG Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]~52 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } "NODE_NAME" } } { "auk_dspip_avalon_streaming_sink.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_sink.vhd" 473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.290 ns ( 44.99 % ) " "Info: Total cell delay = 1.290 ns ( 44.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.577 ns ( 55.01 % ) " "Info: Total interconnect delay = 1.577 ns ( 55.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { data_in fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]~52 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { data_in data_in~combout fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]~52 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } { 0.000ns 0.000ns 1.577ns 0.000ns } { 0.000ns 1.016ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { clock clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { clock clock~combout clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } { 0.000ns 0.000ns 0.179ns 1.104ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { data_in fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]~52 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { data_in data_in~combout fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]~52 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } { 0.000ns 0.000ns 1.577ns 0.000ns } { 0.000ns 1.016ns 0.178ns 0.096ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "108 " "Info: Allocated 108 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 11 09:59:34 2007 " "Info: Processing ended: Tue Sep 11 09:59:34 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}