pie_code.tan.qmsg

pie edcode编码 程序设计

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 216 -40 128 232 "clock" "" } } } } { "f:/program files/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/program files/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register memory fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|empty_dff fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|altsyncram_2lf1:FIFOram\|ram_block1a0~portb_address_reg2 195.01 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 195.01 MHz between source register \"fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|empty_dff\" and destination memory \"fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|altsyncram_2lf1:FIFOram\|ram_block1a0~portb_address_reg2\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.564 ns 2.564 ns 5.128 ns " "Info: fmax restricted to Clock High delay (2.564 ns) plus Clock Low delay (2.564 ns) : restricted to 5.128 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.020 ns + Longest register memory " "Info: + Longest register to memory delay is 4.020 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|empty_dff 1 REG LCFF_X28_Y24_N25 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y24_N25; Fanout = 13; REG Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|empty_dff'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff } "NODE_NAME" } } { "db/a_dpfifo_i551.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/db/a_dpfifo_i551.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.830 ns) + CELL(0.178 ns) 2.008 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|ram_read_address\[2\]~41 2 COMB LCCOMB_X38_Y20_N12 2 " "Info: 2: + IC(1.830 ns) + CELL(0.178 ns) = 2.008 ns; Loc. = LCCOMB_X38_Y20_N12; Fanout = 2; COMB Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|ram_read_address\[2\]~41'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.008 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|ram_read_address[2]~41 } "NODE_NAME" } } { "db/a_dpfifo_i551.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/db/a_dpfifo_i551.tdf" 65 18 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.853 ns) + CELL(0.159 ns) 4.020 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|altsyncram_2lf1:FIFOram\|ram_block1a0~portb_address_reg2 3 MEM M4K_X26_Y24 1 " "Info: 3: + IC(1.853 ns) + CELL(0.159 ns) = 4.020 ns; Loc. = M4K_X26_Y24; Fanout = 1; MEM Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|altsyncram_2lf1:FIFOram\|ram_block1a0~portb_address_reg2'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.012 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|ram_read_address[2]~41 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } "NODE_NAME" } } { "db/altsyncram_2lf1.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/db/altsyncram_2lf1.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.337 ns ( 8.38 % ) " "Info: Total cell delay = 0.337 ns ( 8.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.683 ns ( 91.62 % ) " "Info: Total interconnect delay = 3.683 ns ( 91.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.020 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|ram_read_address[2]~41 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "4.020 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|ram_read_address[2]~41 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } { 0.000ns 1.830ns 1.853ns } { 0.000ns 0.178ns 0.159ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.110 ns - Smallest " "Info: - Smallest clock skew is 0.110 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.031 ns + Shortest memory " "Info: + Shortest clock path from clock \"clock\" to destination memory is 3.031 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 216 -40 128 232 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.179 ns) + CELL(0.000 ns) 1.215 ns clock~clkctrl 2 COMB CLKCTRL_G3 375 " "Info: 2: + IC(0.179 ns) + CELL(0.000 ns) = 1.215 ns; Loc. = CLKCTRL_G3; Fanout = 375; COMB Node = 'clock~clkctrl'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.179 ns" { clock clock~clkctrl } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 216 -40 128 232 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.783 ns) 3.031 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|altsyncram_2lf1:FIFOram\|ram_block1a0~portb_address_reg2 3 MEM M4K_X26_Y24 1 " "Info: 3: + IC(1.033 ns) + CELL(0.783 ns) = 3.031 ns; Loc. = M4K_X26_Y24; Fanout = 1; MEM Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|altsyncram_2lf1:FIFOram\|ram_block1a0~portb_address_reg2'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.816 ns" { clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } "NODE_NAME" } } { "db/altsyncram_2lf1.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/db/altsyncram_2lf1.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.819 ns ( 60.01 % ) " "Info: Total cell delay = 1.819 ns ( 60.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.212 ns ( 39.99 % ) " "Info: Total interconnect delay = 1.212 ns ( 39.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.031 ns" { clock clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.031 ns" { clock clock~combout clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } { 0.000ns 0.000ns 0.179ns 1.033ns } { 0.000ns 1.036ns 0.000ns 0.783ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.921 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 216 -40 128 232 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.179 ns) + CELL(0.000 ns) 1.215 ns clock~clkctrl 2 COMB CLKCTRL_G3 375 " "Info: 2: + IC(0.179 ns) + CELL(0.000 ns) = 1.215 ns; Loc. = CLKCTRL_G3; Fanout = 375; COMB Node = 'clock~clkctrl'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.179 ns" { clock clock~clkctrl } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 216 -40 128 232 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.104 ns) + CELL(0.602 ns) 2.921 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|empty_dff 3 REG LCFF_X28_Y24_N25 13 " "Info: 3: + IC(1.104 ns) + CELL(0.602 ns) = 2.921 ns; Loc. = LCFF_X28_Y24_N25; Fanout = 13; REG Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|scfifo:\\normal_fifo:in_fifo\|scfifo_ded1:auto_generated\|a_dpfifo_i551:dpfifo\|empty_dff'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.706 ns" { clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff } "NODE_NAME" } } { "db/a_dpfifo_i551.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/db/a_dpfifo_i551.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.638 ns ( 56.08 % ) " "Info: Total cell delay = 1.638 ns ( 56.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.283 ns ( 43.92 % ) " "Info: Total interconnect delay = 1.283 ns ( 43.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { clock clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { clock clock~combout clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff } { 0.000ns 0.000ns 0.179ns 1.104ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.031 ns" { clock clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.031 ns" { clock clock~combout clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } { 0.000ns 0.000ns 0.179ns 1.033ns } { 0.000ns 1.036ns 0.000ns 0.783ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { clock clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { clock clock~combout clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff } { 0.000ns 0.000ns 0.179ns 1.104ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "db/a_dpfifo_i551.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/db/a_dpfifo_i551.tdf" 44 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.040 ns + " "Info: + Micro setup delay of destination is 0.040 ns" {  } { { "db/altsyncram_2lf1.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/db/altsyncram_2lf1.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.020 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|ram_read_address[2]~41 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "4.020 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|ram_read_address[2]~41 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } { 0.000ns 1.830ns 1.853ns } { 0.000ns 0.178ns 0.159ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.031 ns" { clock clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.031 ns" { clock clock~combout clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } { 0.000ns 0.000ns 0.179ns 1.033ns } { 0.000ns 1.036ns 0.000ns 0.783ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { clock clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { clock clock~combout clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff } { 0.000ns 0.000ns 0.179ns 1.104ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 } {  } {  } "" } } { "db/altsyncram_2lf1.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/db/altsyncram_2lf1.tdf" 48 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\] data_in clock -0.092 ns register " "Info: tsu for register \"fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\]\" (data pin = \"data_in\", clock pin = \"clock\") is -0.092 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.867 ns + Longest pin register " "Info: + Longest pin to register delay is 2.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.016 ns) 1.016 ns data_in 1 PIN PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(1.016 ns) = 1.016 ns; Loc. = PIN_C13; Fanout = 1; PIN Node = 'data_in'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 248 -40 128 264 "data_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.577 ns) + CELL(0.178 ns) 2.771 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\]~52 2 COMB LCCOMB_X28_Y24_N0 1 " "Info: 2: + IC(1.577 ns) + CELL(0.178 ns) = 2.771 ns; Loc. = LCCOMB_X28_Y24_N0; Fanout = 1; COMB Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\]~52'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.755 ns" { data_in fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]~52 } "NODE_NAME" } } { "auk_dspip_avalon_streaming_sink.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_sink.vhd" 473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.867 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\] 3 REG LCFF_X28_Y24_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 2.867 ns; Loc. = LCFF_X28_Y24_N1; Fanout = 2; REG Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]~52 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } "NODE_NAME" } } { "auk_dspip_avalon_streaming_sink.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_sink.vhd" 473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.290 ns ( 44.99 % ) " "Info: Total cell delay = 1.290 ns ( 44.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.577 ns ( 55.01 % ) " "Info: Total interconnect delay = 1.577 ns ( 55.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { data_in fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]~52 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { data_in data_in~combout fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]~52 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } { 0.000ns 0.000ns 1.577ns 0.000ns } { 0.000ns 1.016ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "auk_dspip_avalon_streaming_sink.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_sink.vhd" 473 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.921 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 216 -40 128 232 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.179 ns) + CELL(0.000 ns) 1.215 ns clock~clkctrl 2 COMB CLKCTRL_G3 375 " "Info: 2: + IC(0.179 ns) + CELL(0.000 ns) = 1.215 ns; Loc. = CLKCTRL_G3; Fanout = 375; COMB Node = 'clock~clkctrl'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.179 ns" { clock clock~clkctrl } "NODE_NAME" } } { "pie_code.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.bdf" { { 216 -40 128 232 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.104 ns) + CELL(0.602 ns) 2.921 ns fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\] 3 REG LCFF_X28_Y24_N1 2 " "Info: 3: + IC(1.104 ns) + CELL(0.602 ns) = 2.921 ns; Loc. = LCFF_X28_Y24_N1; Fanout = 2; REG Node = 'fff:inst1\|fff_new:fff_new_inst\|auk_dspip_avalon_streaming_sink:sink\|at_sink_data_int\[0\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.706 ns" { clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } "NODE_NAME" } } { "auk_dspip_avalon_streaming_sink.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_sink.vhd" 473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.638 ns ( 56.08 % ) " "Info: Total cell delay = 1.638 ns ( 56.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.283 ns ( 43.92 % ) " "Info: Total interconnect delay = 1.283 ns ( 43.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { clock clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { clock clock~combout clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } { 0.000ns 0.000ns 0.179ns 1.104ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { data_in fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]~52 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { data_in data_in~combout fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]~52 fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } { 0.000ns 0.000ns 1.577ns 0.000ns } { 0.000ns 1.016ns 0.178ns 0.096ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { clock clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { clock clock~combout clock~clkctrl fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] } { 0.000ns 0.000ns 0.179ns 1.104ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}