pie_code.map.qmsg

pie edcode编码 程序设计

{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "inv_rst fff_st.v(51) " "Warning (10036): Verilog HDL or VHDL warning at fff_st.v(51): object \"inv_rst\" assigned a value but never read" {  } { { "fff_st.v" "" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 51 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "../../../ip/fir_compiler/lib/tdl_da_lc.v 1 1 " "Warning: Using design file ../../../ip/fir_compiler/lib/tdl_da_lc.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 tdl_da_lc " "Info: Found entity 1: tdl_da_lc" {  } { { "../../../ip/fir_compiler/lib/tdl_da_lc.v" "" { Text "F:/program files/altera/61/ip/fir_compiler/lib/tdl_da_lc.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tdl_da_lc fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|tdl_da_lc:Utdldalc0n " "Info: Elaborating entity \"tdl_da_lc\" for hierarchy \"fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|tdl_da_lc:Utdldalc0n\"" {  } { { "fff_st.v" "Utdldalc0n" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 105 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "../../../ip/fir_compiler/lib/uadd_cen.v 1 1 " "Warning: Using design file ../../../ip/fir_compiler/lib/uadd_cen.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uadd_cen " "Info: Found entity 1: uadd_cen" {  } { { "../../../ip/fir_compiler/lib/uadd_cen.v" "" { Text "F:/program files/altera/61/ip/fir_compiler/lib/uadd_cen.v" 19 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uadd_cen fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|uadd_cen:U_0_sym_add " "Info: Elaborating entity \"uadd_cen\" for hierarchy \"fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|uadd_cen:U_0_sym_add\"" {  } { { "fff_st.v" "U_0_sym_add" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 206 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "../../../ip/fir_compiler/lib/rom_lut_r_cen.v 1 1 " "Warning: Using design file ../../../ip/fir_compiler/lib/rom_lut_r_cen.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 rom_lut_r_cen " "Info: Found entity 1: rom_lut_r_cen" {  } { { "../../../ip/fir_compiler/lib/rom_lut_r_cen.v" "" { Text "F:/program files/altera/61/ip/fir_compiler/lib/rom_lut_r_cen.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|rom_lut_r_cen:Ur0_n_0_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|rom_lut_r_cen:Ur0_n_0_pp\"" {  } { { "fff_st.v" "Ur0_n_0_pp" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 304 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|rom_lut_r_cen:Ur1_n_0_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|rom_lut_r_cen:Ur1_n_0_pp\"" {  } { { "fff_st.v" "Ur1_n_0_pp" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 366 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|rom_lut_r_cen:Ur2_n_0_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|rom_lut_r_cen:Ur2_n_0_pp\"" {  } { { "fff_st.v" "Ur2_n_0_pp" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 424 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|rom_lut_r_cen:Ur3_n_0_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|rom_lut_r_cen:Ur3_n_0_pp\"" {  } { { "fff_st.v" "Ur3_n_0_pp" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 480 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|rom_lut_r_cen:Ur4_n_0_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|rom_lut_r_cen:Ur4_n_0_pp\"" {  } { { "fff_st.v" "Ur4_n_0_pp" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 530 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "../../../ip/fir_compiler/lib/sadd_lpm_cen.v 1 1 " "Warning: Using design file ../../../ip/fir_compiler/lib/sadd_lpm_cen.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sadd_lpm_cen " "Info: Found entity 1: sadd_lpm_cen" {  } { { "../../../ip/fir_compiler/lib/sadd_lpm_cen.v" "" { Text "F:/program files/altera/61/ip/fir_compiler/lib/sadd_lpm_cen.v" 19 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sadd_lpm_cen fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n " "Info: Elaborating entity \"sadd_lpm_cen\" for hierarchy \"fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n\"" {  } { { "fff_st.v" "Uadd_0_lut_l_0_n_0_n" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 576 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sadd_lpm_cen fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|sadd_lpm_cen:Uadd_cen_l_0_n_0_n " "Info: Elaborating entity \"sadd_lpm_cen\" for hierarchy \"fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|sadd_lpm_cen:Uadd_cen_l_0_n_0_n\"" {  } { { "fff_st.v" "Uadd_cen_l_0_n_0_n" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 647 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sadd_lpm_cen fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|sadd_lpm_cen:Uadd_cen_l_1_n_0_n " "Info: Elaborating entity \"sadd_lpm_cen\" for hierarchy \"fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|sadd_lpm_cen:Uadd_cen_l_1_n_0_n\"" {  } { { "fff_st.v" "Uadd_cen_l_1_n_0_n" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 660 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sadd_lpm_cen fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|sadd_lpm_cen:Uadd_cen_l_2_n_0_n " "Info: Elaborating entity \"sadd_lpm_cen\" for hierarchy \"fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|sadd_lpm_cen:Uadd_cen_l_2_n_0_n\"" {  } { { "fff_st.v" "Uadd_cen_l_2_n_0_n" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 669 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "../../../ip/fir_compiler/lib/mac_tl.v 1 1 " "Warning: Using design file ../../../ip/fir_compiler/lib/mac_tl.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 mac_tl " "Info: Found entity 1: mac_tl" {  } { { "../../../ip/fir_compiler/lib/mac_tl.v" "" { Text "F:/program files/altera/61/ip/fir_compiler/lib/mac_tl.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mac_tl fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|mac_tl:Umtl " "Info: Elaborating entity \"mac_tl\" for hierarchy \"fff:inst1\|fff_new:fff_new_inst\|fff_st:fir_core\|mac_tl:Umtl\"" {  } { { "fff_st.v" "Umtl" { Text "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v" 678 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "../../../ip/fir_compiler/lib/par_ctrl.v 1 1 " "Warning: Using design file ../../../ip/fir_compiler/lib/par_ctrl.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 par_ctrl " "Info: Found entity 1: par_ctrl" {  } { { "../../../ip/fir_compiler/lib/par_ctrl.v" "" { Text "F:/program files/altera/61/ip/fir_compiler/lib/par_ctrl.v" 27 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}