pie_code.hier_info

pie edcode编码 程序设计

res[1] <= res[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|uadd_cen:U_18_sym_add
clk => res[0]~reg0.CLK
clk => res[1]~reg0.CLK
gclk_en => res[0]~reg0.ENA
gclk_en => res[1]~reg0.ENA
ain[0] => Add0.IN1
bin[0] => Add0.IN2
res[0] <= res[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
res[1] <= res[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|uadd_cen:U_19_sym_add
clk => res[0]~reg0.CLK
clk => res[1]~reg0.CLK
gclk_en => res[0]~reg0.ENA
gclk_en => res[1]~reg0.ENA
ain[0] => Add0.IN1
bin[0] => Add0.IN2
res[0] <= res[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
res[1] <= res[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|uadd_cen:U_20_sym_add
clk => res[0]~reg0.CLK
clk => res[1]~reg0.CLK
gclk_en => res[0]~reg0.ENA
gclk_en => res[1]~reg0.ENA
ain[0] => Add0.IN1
bin[0] => Add0.IN2
res[0] <= res[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
res[1] <= res[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|uadd_cen:U_21_sym_add
clk => res[0]~reg0.CLK
clk => res[1]~reg0.CLK
gclk_en => res[0]~reg0.ENA
gclk_en => res[1]~reg0.ENA
ain[0] => Add0.IN1
bin[0] => Add0.IN2
res[0] <= res[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
res[1] <= res[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|uadd_cen:U_22_sym_add
clk => res[0]~reg0.CLK
clk => res[1]~reg0.CLK
gclk_en => res[0]~reg0.ENA
gclk_en => res[1]~reg0.ENA
ain[0] => Add0.IN1
bin[0] => Add0.IN2
res[0] <= res[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
res[1] <= res[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|uadd_cen:U_23_sym_add
clk => res[0]~reg0.CLK
clk => res[1]~reg0.CLK
gclk_en => res[0]~reg0.ENA
gclk_en => res[1]~reg0.ENA
ain[0] => Add0.IN1
bin[0] => Add0.IN2
res[0] <= res[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
res[1] <= res[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur0_n_0_pp
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[3]~reg0.CLK
gclk_en => data_out[2]~reg0.ENA
gclk_en => data_out[1]~reg0.ENA
gclk_en => data_out[0]~reg0.ENA
gclk_en => data_out[3]~reg0.ENA
addr_in[0] => Decoder0.IN3
addr_in[0] => Decoder1.IN2
addr_in[1] => Decoder0.IN2
addr_in[2] => Decoder0.IN1
addr_in[2] => Decoder1.IN1
addr_in[3] => Decoder0.IN0
addr_in[3] => Decoder1.IN0
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur0_n_1_pp
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[3]~reg0.CLK
gclk_en => data_out[2]~reg0.ENA
gclk_en => data_out[1]~reg0.ENA
gclk_en => data_out[0]~reg0.ENA
gclk_en => data_out[3]~reg0.ENA
addr_in[0] => Decoder0.IN3
addr_in[0] => Decoder1.IN2
addr_in[1] => Decoder0.IN2
addr_in[2] => Decoder0.IN1
addr_in[2] => Decoder1.IN1
addr_in[3] => Decoder0.IN0
addr_in[3] => Decoder1.IN0
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur1_n_0_pp
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[5]~reg0.CLK
gclk_en => data_out[4]~reg0.ENA
gclk_en => data_out[3]~reg0.ENA
gclk_en => data_out[2]~reg0.ENA
gclk_en => data_out[1]~reg0.ENA
gclk_en => data_out[0]~reg0.ENA
gclk_en => data_out[5]~reg0.ENA
addr_in[0] => Decoder0.IN3
addr_in[1] => Decoder0.IN2
addr_in[1] => Decoder1.IN2
addr_in[2] => Decoder0.IN1
addr_in[2] => Decoder1.IN1
addr_in[3] => Decoder0.IN0
addr_in[3] => Decoder1.IN0
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur1_n_1_pp
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[5]~reg0.CLK
gclk_en => data_out[4]~reg0.ENA
gclk_en => data_out[3]~reg0.ENA
gclk_en => data_out[2]~reg0.ENA
gclk_en => data_out[1]~reg0.ENA
gclk_en => data_out[0]~reg0.ENA
gclk_en => data_out[5]~reg0.ENA
addr_in[0] => Decoder0.IN3
addr_in[1] => Decoder0.IN2
addr_in[1] => Decoder1.IN2
addr_in[2] => Decoder0.IN1
addr_in[2] => Decoder1.IN1
addr_in[3] => Decoder0.IN0
addr_in[3] => Decoder1.IN0
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur2_n_0_pp
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[6]~reg0.CLK
gclk_en => data_out[5]~reg0.ENA
gclk_en => data_out[4]~reg0.ENA
gclk_en => data_out[3]~reg0.ENA
gclk_en => data_out[2]~reg0.ENA
gclk_en => data_out[1]~reg0.ENA
gclk_en => data_out[0]~reg0.ENA
gclk_en => data_out[6]~reg0.ENA
addr_in[0] => Decoder1.IN3
addr_in[1] => Decoder0.IN2
addr_in[1] => Decoder1.IN2
addr_in[1] => Decoder2.IN1
addr_in[2] => Decoder0.IN1
addr_in[2] => Decoder1.IN1
addr_in[3] => Decoder0.IN0
addr_in[3] => Decoder1.IN0
addr_in[3] => Decoder2.IN0
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur2_n_1_pp
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[6]~reg0.CLK
gclk_en => data_out[5]~reg0.ENA
gclk_en => data_out[4]~reg0.ENA
gclk_en => data_out[3]~reg0.ENA
gclk_en => data_out[2]~reg0.ENA
gclk_en => data_out[1]~reg0.ENA
gclk_en => data_out[0]~reg0.ENA
gclk_en => data_out[6]~reg0.ENA
addr_in[0] => Decoder1.IN3
addr_in[1] => Decoder0.IN2
addr_in[1] => Decoder1.IN2
addr_in[1] => Decoder2.IN1
addr_in[2] => Decoder0.IN1
addr_in[2] => Decoder1.IN1
addr_in[3] => Decoder0.IN0
addr_in[3] => Decoder1.IN0
addr_in[3] => Decoder2.IN0
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur3_n_0_pp
clk => data_out[8]~reg0.CLK
clk => data_out[7]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[9]~reg0.CLK
gclk_en => data_out[8]~reg0.ENA
gclk_en => data_out[7]~reg0.ENA
gclk_en => data_out[6]~reg0.ENA
gclk_en => data_out[5]~reg0.ENA
gclk_en => data_out[4]~reg0.ENA
gclk_en => data_out[3]~reg0.ENA
gclk_en => data_out[2]~reg0.ENA
gclk_en => data_out[1]~reg0.ENA
gclk_en => data_out[0]~reg0.ENA
gclk_en => data_out[9]~reg0.ENA
addr_in[0] => Decoder1.IN3
addr_in[0] => Decoder2.IN2
addr_in[0] => Decoder3.IN2
addr_in[1] => Decoder0.IN2
addr_in[1] => Decoder1.IN2
addr_in[1] => Decoder2.IN1
addr_in[1] => Decoder3.IN1
addr_in[2] => Decoder0.IN1
addr_in[2] => Decoder1.IN1
addr_in[2] => Decoder3.IN0
addr_in[3] => Decoder0.IN0
addr_in[3] => Decoder1.IN0
addr_in[3] => Decoder2.IN0
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur3_n_1_pp
clk => data_out[8]~reg0.CLK
clk => data_out[7]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[9]~reg0.CLK
gclk_en => data_out[8]~reg0.ENA
gclk_en => data_out[7]~reg0.ENA
gclk_en => data_out[6]~reg0.ENA
gclk_en => data_out[5]~reg0.ENA
gclk_en => data_out[4]~reg0.ENA
gclk_en => data_out[3]~reg0.ENA
gclk_en => data_out[2]~reg0.ENA
gclk_en => data_out[1]~reg0.ENA
gclk_en => data_out[0]~reg0.ENA
gclk_en => data_out[9]~reg0.ENA
addr_in[0] => Decoder1.IN3
addr_in[0] => Decoder2.IN2
addr_in[0] => Decoder3.IN2
addr_in[1] => Decoder0.IN2
addr_in[1] => Decoder1.IN2
addr_in[1] => Decoder2.IN1
addr_in[1] => Decoder3.IN1
addr_in[2] => Decoder0.IN1
addr_in[2] => Decoder1.IN1
addr_in[2] => Decoder3.IN0
addr_in[3] => Decoder0.IN0
addr_in[3] => Decoder1.IN0
addr_in[3] => Decoder2.IN0
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|rom_lut_r_cen:Ur4_n_0_pp
clk => data_out[14]~reg0.CLK
clk => data_out[13]~reg0.CLK
clk => data_out[12]~reg0.CLK
clk => data_out[11]~reg0.CLK
clk => data_out[10]~reg0.CLK
clk => data_out[9]~reg0.CLK
clk => data_out[8]~reg0.CLK
clk => data_out[7]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => data_out[15]~reg0.CLK
gclk_en => data_out[14]~reg0.ENA
gclk_en => data_out[13]~reg0.ENA
gclk_en => data_out[12]~reg0.ENA
gclk_en => data_out[11]~reg0.ENA
gclk_en => data_out[10]~reg0.ENA
gclk_en => data_out[9]~reg0.ENA
gclk_en => data_out[8]~reg0.ENA
gclk_en => data_out[7]~reg0.ENA
gclk_en => data_out[6]~reg0.ENA
gclk_en => data_out[5]~reg0.ENA
gclk_en => data_out[4]~reg0.ENA
gclk_en => data_out[3]~reg0.ENA
gclk_en => data_out[2]~reg0.ENA
gclk_en => data_out[1]~reg0.ENA
gclk_en => data_out[0]~reg0.ENA
gclk_en => data_out[15]~reg0.ENA
addr_in[0] => Decoder0.IN3
addr_in[0] => Decoder1.IN2
addr_in[0] => Decoder2.IN1
addr_in[1] => Decoder0.IN2
addr_in[2] => Decoder0.IN1
addr_in[2] => Decoder1.IN1
addr_in[3] => Decoder0.IN0
addr_in[3] => Decoder1.IN0
addr_in[3] => Decoder2.IN0
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE