pie_code.hier_info

pie edcode编码 程序设计

|pie_code
data_ready <= fff:inst1.ast_sink_ready
clock => fff:inst1.clk
data_in => fff:inst1.ast_sink_data
data_valid <= fff:inst1.ast_source_valid
data_out[0] <= fff:inst1.ast_source_data[0]
data_out[1] <= fff:inst1.ast_source_data[1]
data_out[2] <= fff:inst1.ast_source_data[2]
data_out[3] <= fff:inst1.ast_source_data[3]
data_out[4] <= fff:inst1.ast_source_data[4]
data_out[5] <= fff:inst1.ast_source_data[5]
data_out[6] <= fff:inst1.ast_source_data[6]
data_out[7] <= fff:inst1.ast_source_data[7]
data_out[8] <= fff:inst1.ast_source_data[8]
data_out[9] <= fff:inst1.ast_source_data[9]
data_out[10] <= fff:inst1.ast_source_data[10]
data_out[11] <= fff:inst1.ast_source_data[11]
data_out[12] <= fff:inst1.ast_source_data[12]
data_out[13] <= fff:inst1.ast_source_data[13]
data_out[14] <= fff:inst1.ast_source_data[14]
data_out[15] <= fff:inst1.ast_source_data[15]
data_out[16] <= fff:inst1.ast_source_data[16]
source_error[0] <= fff:inst1.ast_source_error[0]
source_error[1] <= fff:inst1.ast_source_error[1]


|pie_code|fff:inst1
clk => fff_new:fff_new_inst.clk
reset_n => fff_new:fff_new_inst.reset_n
ast_sink_data => fff_new:fff_new_inst.ast_sink_data
ast_sink_valid => fff_new:fff_new_inst.ast_sink_valid
ast_source_ready => fff_new:fff_new_inst.ast_source_ready
ast_sink_error[0] => fff_new:fff_new_inst.ast_sink_error[0]
ast_sink_error[1] => fff_new:fff_new_inst.ast_sink_error[1]
ast_source_data[0] <= fff_new:fff_new_inst.ast_source_data[0]
ast_source_data[1] <= fff_new:fff_new_inst.ast_source_data[1]
ast_source_data[2] <= fff_new:fff_new_inst.ast_source_data[2]
ast_source_data[3] <= fff_new:fff_new_inst.ast_source_data[3]
ast_source_data[4] <= fff_new:fff_new_inst.ast_source_data[4]
ast_source_data[5] <= fff_new:fff_new_inst.ast_source_data[5]
ast_source_data[6] <= fff_new:fff_new_inst.ast_source_data[6]
ast_source_data[7] <= fff_new:fff_new_inst.ast_source_data[7]
ast_source_data[8] <= fff_new:fff_new_inst.ast_source_data[8]
ast_source_data[9] <= fff_new:fff_new_inst.ast_source_data[9]
ast_source_data[10] <= fff_new:fff_new_inst.ast_source_data[10]
ast_source_data[11] <= fff_new:fff_new_inst.ast_source_data[11]
ast_source_data[12] <= fff_new:fff_new_inst.ast_source_data[12]
ast_source_data[13] <= fff_new:fff_new_inst.ast_source_data[13]
ast_source_data[14] <= fff_new:fff_new_inst.ast_source_data[14]
ast_source_data[15] <= fff_new:fff_new_inst.ast_source_data[15]
ast_source_data[16] <= fff_new:fff_new_inst.ast_source_data[16]
ast_sink_ready <= fff_new:fff_new_inst.ast_sink_ready
ast_source_valid <= fff_new:fff_new_inst.ast_source_valid
ast_source_error[0] <= fff_new:fff_new_inst.ast_source_error[0]
ast_source_error[1] <= fff_new:fff_new_inst.ast_source_error[1]


|pie_code|fff:inst1|fff_new:fff_new_inst
clk => fff_st:fir_core.clk
clk => auk_dspip_avalon_streaming_controller:intf_ctrl.clk
clk => auk_dspip_avalon_streaming_source:source.clk
clk => auk_dspip_avalon_streaming_sink:sink.clk
reset_n => auk_dspip_avalon_streaming_controller:intf_ctrl.reset_n
reset_n => auk_dspip_avalon_streaming_source:source.reset_n
reset_n => auk_dspip_avalon_streaming_sink:sink.reset_n
ast_sink_ready <= auk_dspip_avalon_streaming_sink:sink.at_sink_ready
ast_source_data[0] <= auk_dspip_avalon_streaming_source:source.at_source_data[0]
ast_source_data[1] <= auk_dspip_avalon_streaming_source:source.at_source_data[1]
ast_source_data[2] <= auk_dspip_avalon_streaming_source:source.at_source_data[2]
ast_source_data[3] <= auk_dspip_avalon_streaming_source:source.at_source_data[3]
ast_source_data[4] <= auk_dspip_avalon_streaming_source:source.at_source_data[4]
ast_source_data[5] <= auk_dspip_avalon_streaming_source:source.at_source_data[5]
ast_source_data[6] <= auk_dspip_avalon_streaming_source:source.at_source_data[6]
ast_source_data[7] <= auk_dspip_avalon_streaming_source:source.at_source_data[7]
ast_source_data[8] <= auk_dspip_avalon_streaming_source:source.at_source_data[8]
ast_source_data[9] <= auk_dspip_avalon_streaming_source:source.at_source_data[9]
ast_source_data[10] <= auk_dspip_avalon_streaming_source:source.at_source_data[10]
ast_source_data[11] <= auk_dspip_avalon_streaming_source:source.at_source_data[11]
ast_source_data[12] <= auk_dspip_avalon_streaming_source:source.at_source_data[12]
ast_source_data[13] <= auk_dspip_avalon_streaming_source:source.at_source_data[13]
ast_source_data[14] <= auk_dspip_avalon_streaming_source:source.at_source_data[14]
ast_source_data[15] <= auk_dspip_avalon_streaming_source:source.at_source_data[15]
ast_source_data[16] <= auk_dspip_avalon_streaming_source:source.at_source_data[16]
ast_sink_data[0] => auk_dspip_avalon_streaming_sink:sink.at_sink_data[0]
ast_sink_valid => auk_dspip_avalon_streaming_sink:sink.at_sink_valid
ast_source_valid <= auk_dspip_avalon_streaming_source:source.at_source_valid
ast_source_ready => auk_dspip_avalon_streaming_source:source.at_source_ready
ast_sink_error[0] => auk_dspip_avalon_streaming_sink:sink.at_sink_error[0]
ast_sink_error[1] => auk_dspip_avalon_streaming_sink:sink.at_sink_error[1]
ast_source_error[0] <= auk_dspip_avalon_streaming_source:source.at_source_error[0]
ast_source_error[1] <= auk_dspip_avalon_streaming_source:source.at_source_error[1]


|pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink
clk => scfifo:normal_fifo:in_fifo.clock
clk => sink_start.CLK
clk => at_sink_data_int[0].CLK
clk => at_sink_eop_int.CLK
clk => at_sink_sop_int.CLK
clk => sink_stall_s.CLK
clk => at_sink_ready_s.CLK
clk => packet_error_s[0].CLK
clk => packet_error_s[1].CLK
clk => sink_out_state~0.IN1
clk => sink_state~0.IN1
reset_n => packet_error_s[1].ACLR
reset_n => scfifo:normal_fifo:in_fifo.aclr
reset_n => at_sink_data_int[0].ACLR
reset_n => packet_error_s[0].ACLR
reset_n => at_sink_eop_int.ACLR
reset_n => at_sink_sop_int.ACLR
reset_n => sink_stall_s.ACLR
reset_n => at_sink_ready_s.ACLR
reset_n => sink_start.ACLR
reset_n => sink_out_state~1.IN1
reset_n => sink_state~1.IN1
data[0] <= scfifo:normal_fifo:in_fifo.q[0]
sink_ready_ctrl => fifo_rdreq~0.IN1
sink_ready_ctrl => sink_out_comb~1.IN1
sink_ready_ctrl => sink_out_comb~3.IN1
sink_stall <= sink_stall_int~0.DB_MAX_OUTPUT_PORT_TYPE
packet_error[0] <= packet_error_s[0].DB_MAX_OUTPUT_PORT_TYPE
packet_error[1] <= packet_error_s[1].DB_MAX_OUTPUT_PORT_TYPE
send_sop <= scfifo:normal_fifo:in_fifo.q[1]
send_eop <= scfifo:normal_fifo:in_fifo.q[2]
at_sink_ready <= at_sink_ready_s.DB_MAX_OUTPUT_PORT_TYPE
at_sink_valid => sink_comb_update_1~1.IN1
at_sink_valid => sink_comb_update_1~3.IN1
at_sink_valid => sink_comb_update_1~2.IN1
at_sink_valid => sink_comb_update_1~0.IN1
at_sink_data[0] => at_sink_data_int[0].DATAIN
at_sink_sop => at_sink_sop_int.DATAIN
at_sink_eop => at_sink_eop_int.DATAIN
at_sink_error[0] => sink_next_state~9.OUTPUTSELECT
at_sink_error[0] => sink_next_state~10.OUTPUTSELECT
at_sink_error[0] => sink_next_state~11.OUTPUTSELECT
at_sink_error[0] => sink_next_state~12.OUTPUTSELECT
at_sink_error[0] => packet_error0~0.IN0
at_sink_error[1] => ~NO_FANOUT~


|pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo
data[0] => scfifo_ded1:auto_generated.data[0]
data[1] => scfifo_ded1:auto_generated.data[1]
data[2] => scfifo_ded1:auto_generated.data[2]
q[0] <= scfifo_ded1:auto_generated.q[0]
q[1] <= scfifo_ded1:auto_generated.q[1]
q[2] <= scfifo_ded1:auto_generated.q[2]
wrreq => scfifo_ded1:auto_generated.wrreq
rdreq => scfifo_ded1:auto_generated.rdreq
clock => scfifo_ded1:auto_generated.clock
aclr => scfifo_ded1:auto_generated.aclr
sclr => scfifo_ded1:auto_generated.sclr
empty <= scfifo_ded1:auto_generated.empty
full <= <GND>
almost_full <= scfifo_ded1:auto_generated.almost_full
almost_empty <= <GND>
usedw[0] <= scfifo_ded1:auto_generated.usedw[0]
usedw[1] <= scfifo_ded1:auto_generated.usedw[1]
usedw[2] <= scfifo_ded1:auto_generated.usedw[2]


|pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated
aclr => a_dpfifo_i551:dpfifo.aclr
almost_full <= dffe_af.DB_MAX_OUTPUT_PORT_TYPE
clock => a_dpfifo_i551:dpfifo.clock
clock => dffe_af.CLK
data[0] => a_dpfifo_i551:dpfifo.data[0]
data[1] => a_dpfifo_i551:dpfifo.data[1]
data[2] => a_dpfifo_i551:dpfifo.data[2]
empty <= a_dpfifo_i551:dpfifo.empty
q[0] <= a_dpfifo_i551:dpfifo.q[0]
q[1] <= a_dpfifo_i551:dpfifo.q[1]
q[2] <= a_dpfifo_i551:dpfifo.q[2]
rdreq => a_dpfifo_i551:dpfifo.rreq
sclr => a_dpfifo_i551:dpfifo.sclr
usedw[0] <= a_dpfifo_i551:dpfifo.usedw[0]
usedw[1] <= a_dpfifo_i551:dpfifo.usedw[1]
usedw[2] <= a_dpfifo_i551:dpfifo.usedw[2]
wrreq => a_dpfifo_i551:dpfifo.wreq


|pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo
aclr => cntr_bjb:rd_ptr_msb.aclr
aclr => cntr_oj7:usedw_counter.aclr
aclr => cntr_cjb:wr_ptr.aclr
clock => altsyncram_2lf1:FIFOram.clock0
clock => altsyncram_2lf1:FIFOram.clock1
clock => cntr_bjb:rd_ptr_msb.clock
clock => cntr_oj7:usedw_counter.clock
clock => cntr_cjb:wr_ptr.clock
clock => empty_dff.CLK
clock => full_dff.CLK
clock => low_addressa[2].CLK
clock => low_addressa[1].CLK
clock => low_addressa[0].CLK
clock => rd_ptr_lsb.CLK
clock => usedw_is_0_dff.CLK
clock => usedw_is_1_dff.CLK
clock => wrreq_delay.CLK
data[0] => altsyncram_2lf1:FIFOram.data_a[0]
data[1] => altsyncram_2lf1:FIFOram.data_a[1]
data[2] => altsyncram_2lf1:FIFOram.data_a[2]
empty <= empty_out.DB_MAX_OUTPUT_PORT_TYPE
q[0] <= altsyncram_2lf1:FIFOram.q_b[0]
q[1] <= altsyncram_2lf1:FIFOram.q_b[1]
q[2] <= altsyncram_2lf1:FIFOram.q_b[2]
rreq => altsyncram_2lf1:FIFOram.clocken1
sclr => cntr_bjb:rd_ptr_msb.sclr
sclr => cntr_oj7:usedw_counter.sclr
sclr => cntr_cjb:wr_ptr.sclr
usedw[0] <= cntr_oj7:usedw_counter.q[0]
usedw[1] <= cntr_oj7:usedw_counter.q[1]
usedw[2] <= cntr_oj7:usedw_counter.q[2]
wreq => altsyncram_2lf1:FIFOram.wren_a
wreq => cntr_oj7:usedw_counter.updown
wreq => cntr_cjb:wr_ptr.cnt_en
wreq => wait_state.IN1


|pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clocken1 => ram_block1a0.ENA1
clocken1 => ram_block1a1.ENA1
clocken1 => ram_block1a2.ENA1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.ENA0


|pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|cntr_bjb:rd_ptr_msb
aclr => counter_reg_bit2a[1].ACLR
aclr => counter_reg_bit2a[0].ACLR
clock => counter_reg_bit2a[1].CLK
clock => counter_reg_bit2a[0].CLK
q[0] <= counter_reg_bit2a[0].REGOUT
q[1] <= counter_reg_bit2a[1].REGOUT


|pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|cntr_oj7:usedw_counter
aclr => counter_reg_bit3a[2].ACLR
aclr => counter_reg_bit3a[1].ACLR
aclr => counter_reg_bit3a[0].ACLR
clock => counter_reg_bit3a[2].CLK
clock => counter_reg_bit3a[1].CLK
clock => counter_reg_bit3a[0].CLK
q[0] <= counter_reg_bit3a[0].REGOUT
q[1] <= counter_reg_bit3a[1].REGOUT
q[2] <= counter_reg_bit3a[2].REGOUT
updown => counter_comb_bita0.DATAB
updown => counter_comb_bita1.DATAB
updown => counter_comb_bita2.DATAB


|pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|cntr_cjb:wr_ptr
aclr => counter_reg_bit4a[2].ACLR
aclr => counter_reg_bit4a[1].ACLR
aclr => counter_reg_bit4a[0].ACLR
clock => counter_reg_bit4a[2].CLK
clock => counter_reg_bit4a[1].CLK
clock => counter_reg_bit4a[0].CLK
q[0] <= counter_reg_bit4a[0].REGOUT
q[1] <= counter_reg_bit4a[1].REGOUT
q[2] <= counter_reg_bit4a[2].REGOUT


|pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source
clk => was_stalled.CLK
clk => source_stall_int_d.CLK
clk => first_data.CLK
clk => data_int1[0].CLK
clk => data_int1[1].CLK
clk => data_int1[2].CLK
clk => data_int1[3].CLK
clk => data_int1[4].CLK
clk => data_int1[5].CLK
clk => data_int1[6].CLK
clk => data_int1[7].CLK
clk => data_int1[8].CLK
clk => data_int1[9].CLK
clk => data_int1[10].CLK
clk => data_int1[11].CLK
clk => data_int1[12].CLK
clk => data_int1[13].CLK
clk => data_int1[14].CLK
clk => data_int1[15].CLK
clk => data_int1[16].CLK
clk => data_int[0].CLK
clk => data_int[1].CLK
clk => data_int[2].CLK
clk => data_int[3].CLK
clk => data_int[4].CLK
clk => data_int[5].CLK
clk => data_int[6].CLK
clk => data_int[7].CLK
clk => data_int[8].CLK
clk => data_int[9].CLK
clk => data_int[10].CLK
clk => data_int[11].CLK
clk => data_int[12].CLK
clk => data_int[13].CLK
clk => data_int[14].CLK
clk => data_int[15].CLK
clk => data_int[16].CLK
clk => at_source_error[0]~reg0.CLK
clk => at_source_error[1]~reg0.CLK
clk => at_source_eop_s.CLK
clk => at_source_sop_s.CLK
clk => valid_ctrl_int1.CLK
clk => valid_ctrl_int.CLK
clk => at_source_valid_s.CLK
clk => at_source_data[0]~reg0.CLK
clk => at_source_data[1]~reg0.CLK
clk => at_source_data[2]~reg0.CLK
clk => at_source_data[3]~reg0.CLK
clk => at_source_data[4]~reg0.CLK
clk => at_source_data[5]~reg0.CLK
clk => at_source_data[6]~reg0.CLK
clk => at_source_data[7]~reg0.CLK
clk => at_source_data[8]~reg0.CLK
clk => at_source_data[9]~reg0.CLK
clk => at_source_data[10]~reg0.CLK
clk => at_source_data[11]~reg0.CLK
clk => at_source_data[12]~reg0.CLK
clk => at_source_data[13]~reg0.CLK
clk => at_source_data[14]~reg0.CLK
clk => at_source_data[15]~reg0.CLK
clk => at_source_data[16]~reg0.CLK
clk => source_state~0.IN1
reset_n => data_int1[5].ACLR
reset_n => data_int1[4].ACLR
reset_n => data_int1[3].ACLR
reset_n => data_int1[2].ACLR
reset_n => data_int1[1].ACLR
reset_n => data_int1[0].ACLR
reset_n => first_data.ACLR
reset_n => source_stall_int_d.ACLR
reset_n => was_stalled.ACLR
reset_n => at_source_eop_s.ACLR
reset_n => at_source_sop_s.ACLR
reset_n => at_source_error[1]~reg0.ACLR
reset_n => at_source_error[0]~reg0.ACLR
reset_n => at_source_valid_s.ACLR
reset_n => valid_ctrl_int.ACLR
reset_n => valid_ctrl_int1.ACLR
reset_n => at_source_data[0]~reg0.ACLR
reset_n => at_source_data[1]~reg0.ACLR
reset_n => at_source_data[2]~reg0.ACLR
reset_n => at_source_data[3]~reg0.ACLR