📄 pie_code.ibs
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[IBIS Ver] 3.2
[File Name] pie_code.ibs
[File Rev] 1.4
[Date] September 11, 2007
|
[Source] Altera, Quartus II 6.1
|
[Notes]
| The models are designated as "Final" and have been
| correlated against physical device operation.
Unused IOs which have been assigned as tri-stated inputs or
as outputs driving any signal in Quartus II are represented by the NC.
|
[Disclaimer] Data is for modeling purposes only and is not guaranteed.
|
[Copyright] Copyright (C) 1991-2006 Altera Corporation
|
[Component] EP2C35F672C7_pie_code
[Manufacturer] Altera Corporation
[Package]
| RLC values are for 672 FBGA package
|variable typ min max
R_pkg 310.00m 120.00m 780.00m
L_pkg 5.06nH 2.07nH 10.18nH
C_pkg 0.90pF 0.55pF 1.95pF
|
[Pin] signal_name model_name R_pin L_pin C_pin
|
A2 GND GND
A3 VCCIO3 POWER
A11 VCCIO3 POWER
A12 GND GND
A15 GND GND
A16 VCCIO4 POWER
A17 data_out[2] 2c_ttl33_cio_d24
A24 VCCIO4 POWER
A25 GND GND
AA8 VCCA_PLL1 POWER
AA19 VCCA_PLL4 POWER
AA21 GND_PLL4 GND
AA22 VCCIO6 POWER
AB5 VCCIO1 POWER
AB6 VCCIO8 POWER
AB7 GND GND
AB9 VCCIO8 POWER
AB11 GND GND
AB13 VCCIO8 POWER
AB14 VCCIO7 POWER
AB16 GND GND
AB17 VCCIO7 POWER
AB19 GND GND
AB22 VCCIO7 POWER
AC4 GND GND
AC15 data_out[16] 2c_ttl33_cio_d24
AC24 NC NC
AD1 VCCIO1 POWER
AD9 GND GND
AD14 GND GND
AD18 GND GND
AD20 VCCIO7 POWER
AD26 VCCIO6 POWER
AE1 GND GND
AE16 data_out[7] 2c_ttl33_cio_d24
AE26 GND GND
AF2 GND GND
AF3 VCCIO8 POWER
AF11 VCCIO8 POWER
AF12 GND GND
AF15 GND GND
AF16 VCCIO7 POWER
AF24 VCCIO7 POWER
AF25 GND GND
B1 GND GND
B17 data_out[4] 2c_ttl33_cio_d24
B26 GND GND
C1 VCCIO2 POWER
C13 data_in 2c_ttl33_cin
C14 GND GND
C16 data_out[10] 2c_ttl33_cio_d24
C18 GND GND
C20 VCCIO4 POWER
C26 VCCIO5 POWER
D4 GND GND
D16 data_out[6] 2c_ttl33_cio_d24
D22 VCCIO4 POWER
D24 GND GND
E4 GND_PLL3 GND
E6 VCCIO3 POWER
E7 GND GND
E9 VCCIO3 POWER
E11 GND GND
E13 VCCIO3 POWER
E14 VCCIO4 POWER
E15 data_out[14] 2c_ttl33_cio_d24
E16 GND GND
E17 VCCIO4 POWER
E19 GND GND
E21 GND_PLL2 GND
E26 source_error[1] 2c_ttl33_rio_d24
F5 VCCIO2 POWER
F8 NC NC
F16 data_out[1] 2c_ttl33_cio_d24
F19 NC NC
F22 VCCIO5 POWER
G7 GND_PLL3 GND
G8 VCCA_PLL3 POWER
G19 VCCA_PLL2 POWER
G20 GND_PLL2 GND
H5 GND GND
H7 VCCD_PLL3 POWER
H9 VCCIO3 POWER
H13 GND GND
H14 GND GND
H18 VCCIO4 POWER
H20 VCCD_PLL2 POWER
H22 GND GND
J7 source_error[0] 2c_ttl33_rio_d24
J11 data_ready 2c_ttl33_cio_d24
J12 VCCIO3 POWER
J15 VCCIO4 POWER
J19 VCCIO5 POWER
K10 NC NC
K11 NC NC
K12 NC NC
K13 NC NC
K14 NC NC
K15 NC NC
K20 GND GND
L1 VCCIO2 POWER
L5 GND GND
L11 NC NC
L12 GND GND
L13 GND GND
L14 GND GND
L15 GND GND
L16 NC NC
L17 NC NC
L18 NC NC
L22 GND GND
L26 VCCIO5 POWER
M1 GND GND
M9 VCCIO2 POWER
M10 NC NC
M11 NC NC
M12 GND GND
M13 GND GND
M14 GND GND
M15 GND GND
M16 NC NC
M17 NC NC
M18 VCCIO5 POWER
M19 data_out[13] 2c_ttl33_rio_d24
M20 data_out[15] 2c_ttl33_rio_d24
M24 data_out[11] 2c_ttl33_rio_d24
M25 data_out[3] 2c_ttl33_rio_d24
M26 GND GND
N5 VCCIO2 POWER
N8 GND GND
N10 NC NC
N11 GND GND
N12 GND GND
N13 GND GND
N14 GND GND
N15 GND GND
N16 GND GND
N17 NC NC
N19 GND GND
N21 NC NC
N22 VCCIO5 POWER
N24 data_valid 2c_ttl33_rio_d24
P2 clock 2c_ttl33_rin
P5 VCCIO1 POWER
P8 GND GND
P10 NC NC
P11 GND GND
P12 GND GND
P13 GND GND
P14 GND GND
P15 GND GND
P16 GND GND
P19 GND GND
P22 VCCIO6 POWER
P23 data_out[12] 2c_ttl33_rio_d24
P24 data_out[9] 2c_ttl33_rio_d24
R1 GND GND
R9 VCCIO1 POWER
R10 NC NC
R11 NC NC
R12 GND GND
R13 GND GND
R14 GND GND
R15 GND GND
R16 NC NC
R18 VCCIO6 POWER
R21 GND GND
R26 GND GND
T1 VCCIO1 POWER
T5 GND GND
T11 NC NC
T12 GND GND
T13 GND GND
T14 GND GND
T15 GND GND
T16 NC NC
T26 VCCIO6 POWER
U8 GND GND
U11 NC NC
U13 NC NC
U14 NC NC
U15 NC NC
U16 NC NC
U19 GND GND
V8 VCCIO1 POWER
V12 VCCIO8 POWER
V15 VCCIO7 POWER
V16 NC NC
V19 VCCIO6 POWER
W5 GND GND
W7 GND_PLL1 GND
W9 VCCIO8 POWER
W13 GND GND
W14 GND GND
W15 data_out[5] 2c_ttl33_cio_d24
W16 data_out[8] 2c_ttl33_cio_d24
W18 VCCIO7 POWER
W20 GND_PLL4 GND
W22 GND GND
Y2 NC NC
Y6 GND_PLL1 GND
Y7 VCCD_PLL1 POWER
Y8 NC NC
Y9 GND GND
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